CD74ACT297M集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

CD74ACT297M属于集成电路（IC）的时钟发生器PLL频率合成器。由美国德州仪器公司制造生产的CD74ACT297M时钟发生器，PLL，频率合成器时钟发生器、PLL 和频率合成器集成电路 (IC) 可为逻辑器件提供参考信号的稳定定时脉冲，这些器件包括计算机、微控制器、数据通信系统和图形/视频发生器。这些集成电路可能包括缓冲器、驱动器、分频器、倍频器、多路复用器、合成器、扇出分配器和预分频器。

Speed of Bipolar FCT, AS, and S, With

Significantly Reduced Power Consumption

Digital Design Avoids Analog

Compensation Errors

Easily Cascadable for Higher-Order Loops

Useful Frequency Range

– DC to 110 MHz Typical (K CLK)

– DC to 70 MHz Typical (I/D CLK)

Dynamically Variable Bandwidth

Very Narrow Bandwidth Attainable

Power-On Reset

Output Capability

– Standard: XORPD OUT, ECPD OUT

– Bus Driver: I/D OUT

SCR Latch-Up-Resistant CMOS Process

and Circuit Design

Balanced Propagation Delays

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015

description/ordering information

The CD74ACT297 provides a simple, cost-effective solution to high-accuracy, digital, phase-locked-loop

applications. This device contains all the necessary circuits, with the exception of the divide-by-N counter, to

build first-order phase-locked loops as shown in Figure 1.

Both exclusive-OR phase detectors (XORPDs) and edge-controlled (ECPD) phase detectors are provided for

maximum flexibility.

Proper partitioning of the loop function, with many of the building blocks external to the package, makes it easy

for the designer to incorporate ripple cancellation or to cascade to higher-order phase-locked loops.

The length of the up/down K counter is digitally programmable according to the K-counter function table. With

A, B, C, and D all low, the K counter is disabled. With A high and B, C, and D low, the K counter is only three

stages long, which widens the bandwidth, or capture range, and shortens the lock time of the loop. When A,

B, C, and D are programmed high, the K counter becomes 17 stages long, which narrows the bandwidth, or

capture range, and lengthens the lock time. Real-time control of loop bandwidth by manipulating the

A-through-D inputs can maximize the overall performance of the digital phase-locked loop.