CD74AC138中文资料3 线至 8 线反向解码器/多路解复用器数据手册TI规格书

描述 Description

The ’AC138 decoders/demultiplexers are designed for high-performance memory-decoding and data-routing applications that require very short propagation-delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications (see Application Information).

特性 Features

• AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Voltage
• Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption
• Designed Specifically for High-Speed Memory Decoders and Data-Transmission Systems
• Incorporate Three Enable Inputs to Simplify Cascading and/or Data Reception
• Balanced Propagation Delays
• ±24-mA Output Drive Current
• Fanout to 15 F Devices

• SCR-Latchup-Resistant CMOS Process and Circuit Design
• Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015

简介

CD74AC138属于集成电路（IC）的信号开关多路复用器解码器。由TI制造生产的CD74AC138信号开关，多路复用器，解码器逻辑型信号开关、多路复用器和编码器 IC 可用于对以数字格式表示数据的电信号进行路由和选择。这些器件与设计用于模拟信号的类似产品有所不同，它们保留的信息表示为两个电状态之一，而不是两个外部界限内的无穷变化量。