CD54HC280F3A.A中文资料德州仪器数据手册PDF规格书

特性 Features

• Typical Propagation Delay = 17ns at VCC = 5V,

CL = 15pF, TA = 25oC

• Replaces LS180 Types

• Easily Cascadable

• Fanout (Over Temperature Range)

- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55oC to 125oC

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: NIL = 30%, NIH = 30% of VCC

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

VIL= 0.8V (Max), VIH = 2V (Min)

- CMOS Input Compatibility, Il ≤ 1μA at VOL, VOH

描述 Description

The ’HC280 and ’HCT280 are 9-bit odd/even parity, generator

checker devices. Both even and odd parity outputs are

available for checking or generating parity for words up to nine

bits long. Even parity is indicated (ΣE output is high) when an

even number of data inputs is high. Odd parity is indicated

(ΣO output is high) when an odd number of data inputs is

high. Parity checking for words larger than 9 bits can be

accomplished by tying the ΣE output to any input of an

additional HC/HCT280 parity checker.