CD54HC280中文资料高速 CMOS 逻辑 9 位奇偶校验发生器/校验器数据手册TI规格书

描述 Description

The ’HC280 and ’HCT280 are 9-bit odd/even parity, generator checker devices. Both even and odd parity outputs are available for checking or generating parity for words up to nine bits long. Even parity is indicated (E output to any input of an additional HC/HCT280 parity checker.

特性 Features

• Typical Propagation Delay = 17ns at VCC = 5V, CL = 15pF, TA = 25°C
• Easily Cascadable
• Bus Driver Outputs...15 LSTTL Loads
• Balanced Propagation Delay and Transition Times
• HC Types
• High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
• Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
• CMOS Input Compatibility, Il 1µA at VOL, VOH
Data sheet acquired from Harris Semiconductor