CD54HC138数据手册TI中文资料规格书

描述 Description

The ’HC138, ’HC238, ’HCT138, and ’HCT238 are high speed silicon gate CMOS decoders well suited to memory address decoding or data routing applications. Both circuits feature low power consumption usually associated with CMOS circuitry, yet have speeds comparable to low power Schottky TTL logic. Both circuits have three binary select inputs (A0, A1 and A2). If the device is enabled, these inputs determine which one of the eight normally high outputs of the HC/HCT138 series will go low or which of the normally low outputs of the HC/HCT238 series will go high.

Two active low and one active high enables (E1\\, E2\\, and E3) are provided to ease the cascading of decoders. The decoder’s 8 outputs can drive 10 low power Schottky TTL equivalent loads.

特性 Features

• Select One Of Eight Data Outputs Active Low for 138, Active High for 238
• I/O Port or Memory Selector
• Three Enable Inputs to Simplify Cascading
• Typical Propagation Delay of 13ns at VCC = 5V, CL = 15pF, TA = 25°C
• Fanout (Over Temperature Range)
• Standard Outputs . . . . 10 LSTTL Loads
• Bus Driver Outputs . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . –55°C to 125°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types
• 2V to 6V Operation
• High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V

• HCT Types
• 4.5V to 5.5V Operation
• Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
• CMOS Input Compatibility, Il 1µA at VOL, VOH

Data sheet acquired from Harris Semiconductor