CD4068BMS中文资料INTERSIL数据手册PDF规格书

描述 Description

CD4068BMS NAND/AND gate provides the system designer with direct implementation of the positive logic 8 Input NAND and AND functions and supplements the existing family of CMOS gates.

特性 Features

• High Voltage Type (20V Rating)

• Medium Speed Operation

- TPHL, TPLH = 75ns (Typ.) at VDD = 10V

• Buffered Inputs and Outputs

• 5V, 10V and 15V Parametric Ratings

• Standardized Symmetrical Output Characteristics

• 100 Tested for Quiescent Current at 20V

• Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25°C

• Noise Margin (Over Full Package/Temperature Range)

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V