CD4068B-MIL数据手册TI中文资料规格书

描述 Description

CD4068B NAND/AND gate provides the system designer with direct implementation of the positive-logic 8-input NAND and AND functions and supplements the existing family of CMOS gates.
The CD4068B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix),14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes),and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

特性 Features

• Medium Speed Operation:    tPHL, tPLH=75 ns (typ.) at VDD = 10 V
• Buffered inputs and outputs
• 5-V, 10-V, and 15-V parametric ratings
• Standardized symmetrical output characteristics
• 100% tested for quiescent current at 20 V
• Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
• Noise margin (over full package-temperature range) =      1 V at VDD = 5 V      2 V at VDD = 10 V   2.5 V at VDD = 15 V
• Meets all requirements of JEDEC Tentative Standard No. 13B, \"Standard Specifications for Description of ’B’ Series CMOS Devices\"
Data sheet acquired from Harris Semiconductor