CD4046B集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

Features:

Very low power consumption:

70 4W (typ.) at VCO f, = 10 kHz, Vpp = 5 V

= Operating frequency range up to 1.4 MHz (typ.)

atVpp=10V, RI =5kQ

Low frequency drift: 0.04%/°C (typ.) at Vpp = 10 V

Choice of two phase comparators:

Exclusive-OR network (1)

Edge-controlled memory network with phase-pulse

output for lock indication (11)

High VCO linearity: <1% (typ.) at Vpp = 10 V

VCO inhibit control for ON-OFF keying

and ultra-low standby power con-

sumption -

Source-follower output of VCO control

input (Demod. output)

Zener diode to assist supply regulation

Standardized, symmetrical output

characteristics

= 100% tested for quiescent current at 20 V

=5-V, 10-V, and 15-V parametric ratings

Meets ail requirements of JEDEC Tentative

Standard No. 138, “Standard Specifications

for Description of ‘B’ Series CMOS Devices