CD4043BF3A中文资料德州仪器数据手册PDF规格书

Features:

3-state outputs with common output

ENABLE

Separate SET and RESET inputs for

each latch

NOR and NAND configurations

5.V, 10-V, and 15-V parametric ratings

= Standardized symmetrical output

characteristics

100% tested for quiescent current at 20 V

Maximum input current of 1 uA at 18 V over

full package temperature range; 100 nA at

18 V and 25°C

Noise margin (over full package temperature

range): 1VatVpp=5V

2VatVpp=10V

25VatVpp=15V

Meets all requirements of JEDEC Tentative

Standard No. 138, ‘‘Standard Specifications

for Description of ‘B’ Series CMOS Devices”