丝印：CD4035BF；Package：CDIP；CMOS 4-Stage Parallel In/Parallel Out Shift Register

Features: ® 4-Stage clocked shift operation # Synchronous parallel entry on all 4 stages a JK inputs on first stage ® Asynchronous True/Complement control on all outputs ® Static flip-flop operation; Master-slave configuration ® Buffered inputs and outputs ® High speed — 12

文件：710.52 Kbytes 页数：17 Pages

TI

德州仪器

丝印：CD4035BF；Package：CDIP；CMOS 4-Stage Parallel In/Parallel Out Shift Register

Features: ® 4-Stage clocked shift operation # Synchronous parallel entry on all 4 stages a JK inputs on first stage ® Asynchronous True/Complement control on all outputs ® Static flip-flop operation; Master-slave configuration ® Buffered inputs and outputs ® High speed — 12

文件：710.52 Kbytes 页数：17 Pages

TI

德州仪器

丝印：CD4035BF；Package：CDIP；CMOS 4-Stage Parallel In/Parallel Out Shift Register

Features: ® 4-Stage clocked shift operation # Synchronous parallel entry on all 4 stages a JK inputs on first stage ® Asynchronous True/Complement control on all outputs ® Static flip-flop operation; Master-slave configuration ® Buffered inputs and outputs ® High speed — 12

文件：710.52 Kbytes 页数：17 Pages

TI

德州仪器

丝印：CD4035BF；Package：CDIP；CMOS 4-Stage Parallel In/Parallel Out Shift Register

Features: ® 4-Stage clocked shift operation # Synchronous parallel entry on all 4 stages a JK inputs on first stage ® Asynchronous True/Complement control on all outputs ® Static flip-flop operation; Master-slave configuration ® Buffered inputs and outputs ® High speed — 12

文件：710.52 Kbytes 页数：17 Pages

TI

德州仪器

丝印：8101701EA；Package：CDIP；CMOS 4-Stage Parallel In/Parallel Out Shift Register

Features: ® 4-Stage clocked shift operation # Synchronous parallel entry on all 4 stages a JK inputs on first stage ® Asynchronous True/Complement control on all outputs ® Static flip-flop operation; Master-slave configuration ® Buffered inputs and outputs ® High speed — 12

文件：710.52 Kbytes 页数：17 Pages

TI

德州仪器

丝印：8101701EA；Package：CDIP；CMOS 4-Stage Parallel In/Parallel Out Shift Register

Features: ® 4-Stage clocked shift operation # Synchronous parallel entry on all 4 stages a JK inputs on first stage ® Asynchronous True/Complement control on all outputs ® Static flip-flop operation; Master-slave configuration ® Buffered inputs and outputs ® High speed — 12

文件：710.52 Kbytes 页数：17 Pages

TI

德州仪器

CMOS 4-STAGE PARALLEL IN/PARALLEL OUT SHIFT REGISTER

文件：269.47 Kbytes 页数：6 Pages

TI

德州仪器

Parallel In/Parallel Out Shift Refister

文件：893.49 Kbytes 页数：17 Pages

TI

德州仪器

CMOS 4-stage Paraller in/Paraller Out shift Register

文件：906.35 Kbytes 页数：16 Pages

TI

德州仪器

Parallel In/Parallel Out Shift Refister

文件：893.49 Kbytes 页数：17 Pages

TI

德州仪器