CD4015BF3A.A中文资料德州仪器数据手册PDF规格书

Features:

® Medium speed operation . ............

12 MHz (typ.) clock rate at Vpp — Vgg = 10 V

® Fully static operation

® 8 master-slave flip-flops plus input and output buffering

® 100% tested for quiescent current at 20 V

®5.V, 10-V, and 15-V parametric ratings

® Standardized, symmetrical output characteristics

= Maximum input current of 1 uA at 18 V

over full package-temperature range;

100 nA at 18 V and 25°C

® Noise margin (full package-temperature

range) =

1VatVpp=5V

2VatVpp=10V

25VatVpp=15V

@ Meets all requirements of JEDEC Tentative

Standard No. 138, “Standard Specifications

for Description of ‘B” Series CMOS Devices”