CD40109B-Q1中文资料德州仪器数据手册PDF规格书

Features:

Independence of power supply sequence

considerations—V cc can exceed Vp, input

signals can exceed both Ve and Vpp

Up and down level-shifting capability

Three-state outputs with seperate enable controls

Standardized, symmetrical output characteristics

100% tested for quiescent current at 20 V

Maximum input current of 1 uA at 18 V

over full package-temperature range;

100 nA at 18 V and 26°C

Noise margin (full package-temperature

range)

=1VatVec=5V,Vpp=10V

=2VatVec=10V,Vpp=16V

5.V, 10-V, and 15-V parametric ratings

Meets all requirements of JEDEC Tentative

Standard No. 138, “Standard Specifications

for Description of ‘B’ Series CMOS Devices”