CAXC4T245QRSVRQ1集成电路（IC）的缓冲器驱动器接收器收发器规格书PDF中文资料

1 Features

• AEC-Q100 qualified for automotive applications

• Available in wettable flank QFN (WBQB) package

• Fully-configurable dual-rail design allows each port

to operate with a power supply range from 0.65 V

to 3.6 V

• Operating temperature from –40°C to +125°C

• Multiple direction control pins to allow

simultaneous up and down translation

• Glitch-free power supply sequencing

• Up to 380 Mbps support when translating from 1.8

V to 3.3 V

• VCC isolation feature:

– If either VCC input is below 100 mV, all

I/O outputs are disabled and become high

impedance

• Ioff supports partial-power-down mode operation

• Compatible with AVC-family level shifters

• Latch-up performance exceeds 100 mA per JESD

78, class II

• ESD protection exceeds JEDEC JS-001

– 8000-V human-body model

– 1000-V charged-device model

2 Applications

• Infotainment head unit

• ADAS fusion

• ADAS front camera

• Hybrid electric vehicles and electric vehicles

battery management system

• Telematics control unit

3 Description

The SN74AXC4T245-Q1 AEC-Q100 qualified device

is a four-bit non-inverting bus transceiver that uses

two individually configurable power-supply rails. The

device is operational with both VCCA and VCCB

supplies as low as 0.65 V. The A port is designed

to track VCCA, which accepts any supply voltage from

0.65 V to 3.6 V. The B port is designed to track

VCCB, which also accepts any supply voltage from

0.65 V to 3.6 V. Additionally the SN74AXC4T245-Q1

is compatible with a single-supply system.

The SN74AXC4T245-Q1 device is designed for

asynchronous communication between data buses.

The device transmits data from the A bus to the B bus

or from the B bus to the A bus, depending on the logic

level of the direction-control inputs (1DIR and 2DIR).

The output-enable inputs (1 OE and 2 OE) are used

to disable the outputs so the buses are effectively

isolated. The SN74AXC4T245-Q1 device is designed

so the control pins (xDIR and x OE) are referenced to

VCCA.

To ensure the high-impedance state of the level shifter

I/Os during power up or power down, the x OE pins

should be tied to VCCA through a pull-up resistor.

This device is fully specified for partial-power-down

applications using the Ioff current. The Ioff protection

circuitry ensures that no excessive current is drawn

from or to an input, output, or combined I/O that

is biased to a specific voltage while the device is

powered down.

The VCC isolation feature ensures that if either VCCA

or VCCB is less than 100 mV, both I/O ports enter a

high-impedance state by disabling their outputs.

Glitch-Free power supply sequencing allows either

supply rail to be powered on or off in any order while

providing robust power sequencing performance.