C8051F231集成电路（IC）的微控制器规格书PDF中文资料

Analog Peripherals

Two comparators

- Programmable hysteresis

- Configurable to generate interrupts or reset

VDD Monitor and Brown-out Detector

On-Chip JTAG Debug

- On-chip emulation circuitry facilitates full-speed, non-intrusive, in-circuit emulation

- Supports breakpoints, single stepping, watchpoints, inspect/modify memory, and registers

- Superior performance to emulation systems using ICE-chips, target pods, and sockets

- Fully compliant with IEEE 1149.1 specification

Supply Voltage: 2.7 to 3.6 V

- Typical operating current: 9 mA at 25 MHz

- Typical stop mode current:

Temperature Range: –40 to +85 °C

High-Speed 8051 µC Core

- Pipelined instruction architecture; executes 70 of instructions in 1 or 2 system clocks

- Up to 25 MIPS throughput with 25 MHz system clock

- Expanded interrupt handler; up to 21 interrupt sources

Memory

- 256 bytes data RAM

- 8 kB Flash; in-system programmable in 512 byte sectors (512 bytes are reserved)

Digital Peripherals

- 22 port I/O; all are 5 V tolerant

- Hardware SPI™ and UART serial ports available concurrently

- 3 general-purpose 16-bit counter/timers

- Dedicated watchdog timer; bidirectional reset

Clock Sources

- Internal programmable oscillator: 2–16 MHz

- External oscillator: Crystal, RC, C, or Clock

- Can switch between clock sources on-the-fly

Package

- 32-pin LQFP (standard lead and lead-free packages)

Part Ordering Numbers

- Lead-free package: C8051F231-GQ

- Standard package: C8051F231