C8051F040DK开发板套件编程器的评估板-嵌入式-MCUDSP规格书PDF中文资料

[Silicon Laboratories]

System Overview

The C8051F04x family of devices are fully integrated mixed-signal System-on-a-Chip MCUs with 64 digital I/O pins (C8051F040/2/4/6) or 32 digital I/O pins (C8051F041/3/5/7), and an integrated CAN 2.0B controller. Highlighted features are listed below; refer to Table 1.1 for specific product feature selection.

• High-Speed pipelined 8051-compatible CIP-51 microcontroller core (up to 25 MIPS)

• Controller Area Network (CAN 2.0B) Controller with 32 message objects, each with its own indentifier mask.

• In-system, full-speed, non-intrusive debug interface (on-chip)

• True 12-bit (C8051F040/1) or 10-bit (C8051F042/3/4/5/6/7) 100 ksps 8-channel ADC with PGA and analog multiplexer

• High Voltage Difference Amplifier input to the 12/10-bit ADC (60 V Peak-to-Peak) with programmable gain.

• True 8-bit 500 ksps 8-channel ADC with PGA and analog multiplexer (C8051F040/1/2/3)

• Two 12-bit DACs with programmable update scheduling (C8051F040/1/2/3)

• 64 kB (C8051F040/1/2/3/4/5) or 32 kB (C8051F046/7) of in-system programmable Flash memory

• 4352 (4096 + 256) bytes of on-chip RAM

• External Data Memory Interface with 64 kB address space

• SPI, SMBus/I2C, and (2) UART serial interfaces implemented in hardware

• Five general purpose 16-bit Timers

• Programmable Counter/Timer Array with six capture/compare modules

• On-chip Watchdog Timer, VDD Monitor, and Temperature Sensor