C3-PLL-2中文资料Phase-locked Loop (PLL) Frequency Synthesizer IP Core数据手册CologneChip规格书
C3-PLL-2规格书详情
描述 Description
The C3-PLL-2 is based on the DIGICCTM technology of Cologne Chip, which makes it possible to be easily implemented in all kinds of digital CMOS circuits as a fully digital circuit using standard cell libraries. The used circuit area is smaller than that of competing technologies. Furthermore the lock time is very short and it is even super-fast when the PLL is restarted after standby mode