AZ100EL32D中文资料ECL/PECL ÷ 2 Divider数据手册Arizona规格书

描述 Description

DESCRIPTION
The AZ10/100EL32 is an integrated ÷2 divider. The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flop will attain a random logic state; the reset allows for the synchronization of multiple EL32’s in a system.
The EL32 provides a VBB output for single-ended use or a DC bias reference for AC coupling to the device. For single-ended input applications, the VBB reference should be connected to one side of the CLK/CLK ¯¯¯¯ differential input pair. The input signal is then fed to the other CLK/CLK ¯¯¯¯ input. The VBB pin should be used only as a bias for the EL32 as its sink/source capability is limited. When used, the VBB pin should be bypassed to ground via a 0.01μF capacitorFEATURES
• 510ps Propagation Delay
• 3.0GHz Toggle Frequency
• High Bandwidth Output Transitions
• 75kΩ Internal Input Pulldown Resistors
• Direct Replacement for ON Semiconductor MC10EL32 & MC100EL32

特性 Features

• 510ps Propagation Delay
• 3.0GHz Toggle Frequency
• High Bandwidth Output Transitions
• 75kΩ Internal Input Pulldown Resistors
• Direct Replacement for ON Semiconductor MC10EL32 & MC100EL32