ATSAM4LC4A数据手册Microchip中文资料规格书

描述 Description

A member of the Microchip's SAM4L family of flash microcontrollers based on the ARM® Cortex®-M4 processor, the ATSAM4LC4A delivers the lowest power in active mode (90uA/MHz) as well as sleep mode (1.5uA) and the shortest wake-up time (down to 1.5us) in a Cortex-M4-based device. Along with 256KB of embedded flash memory, the device features an LCD controller, hardware cryptography, USB host and device, peripheral event system, SleepWalking intelligent peripherals, and built-in security, including 128-bit Advanced Encryption Standard (AES). Integrated Microchip QTouch technology makes it easy to bring capacitive touch functionality to your hardware.

特性 Features

Microcontroller FeaturesCore
• ARM Cortex-M4 running at up to 48 MHz
• Memory Protection Unit (MPU)
• DSP Instructions, Thumb®-2 instruction set
Memories
• 256 Kbytes embedded Flash, 0 wait-state capability up to 24MHz
• 32 Kbytes embedded SRAM
System
• Embedded voltage regulator for single-supply operation
• Two Power-on-Reset and Two Brown-out Detectors (BOD)
• Quartz or ceramic resonator oscillators: 0.6 to 30MHz main power with Failure Detection and low power 32.768 kHz for RTC or device clock
• High-precision 8/12 MHz factory-trimmed internal RC oscillator
• Slow clock internal RC oscillator as permanent low-power mode device clock
• High speed 80MHz internal RC oscillator
• Low power 32kHz internal RC oscillator
• PLL up to 240MHz for device clock and for USB
• Digital Frequency Locked Loop (DFLL) with wide input range
• Up to 16 peripheral DMA (PDCA) channels
picoPower® Technology for Ultra-low Power Consumption
• Active mode down to 90μA/MHz with configurable voltage scaling
• High performance and efficiency: 28 coremark/mA
• Wait mode down to 3μA with fast wake-up time (<1.5μs) supporting SleepWalking
• Full RAM and Logic Retention mode down to 1.5μA with fast wake-up time (<1.5μs)
• Ultra low power Backup mode with/without RTC down to 1.5/0.9μA
Package
• 48-lead LQFP, 7x7 mm, pitch 0.5 mm
• 48-pad QFN, 7x7 mm, pitch 0.5 mm
Temperature operating range
• Industrial (-40° C to +85° C)
Peripheral Features
• USB 2.0 Device and Embedded Host: 12 Mbps, up to 8 bidirectional Endpoints and Multi-packet Ping-pong Mode. On-Chip Transceiver
• One USART with ISO7816, IrDA®, RS-485, SPI, Manchester and LIN Mode
• Two USART with SPI Mode
• Liquid Crystal Display (LCD) Module with Capacity up to 40 Segments and up to 4 Common Terminals
• Windowed Watchdog Timer (WDT)
• Asynchronous Timer (AST) with Real-time Clock Capability, Counter or Calendar Mode Supported
• Frequency Meter (FREQM) for Accurate Measuring of Clock Frequency
• Three 16-bit Timer/Counter (TC) Channels with capture, waveform, compare and PWM mode
• One Master/Slave Serial Peripheral Interface (SPI) with Chip Select Signals
• Two Master and One Slave Two-wire Interfaces (TWI), up to 3.4Mbit/s I2C-compatible
• Capacitive Touch Module (CATB) supporting up to 32 buttons
• Inter-IC Sound (IISC) Controller, Compliant with Inter-IC Sound (I2S) Specification
• Peripheral Event System for Direct Peripheral to Peripheral Communication
• Parallel Capture Module (PARC)
• Glue Logic Controller (GLOC)
I/O
• 27 I/O lines with external interrupt capability (edge or level sensitivity), debouncing, glitch filtering and slew-rate control
• One High-drive I/O Pins
Analog Features
• One 4-channel ADC 300Ksps (ADC) with up to 12 Bits Resolution
• One DAC 500Ksps (DACC) with up to 10 Bits Resolution
• One Analog Comparators (ACIFC) with Optional Window Detection
• Audio Bitstream DAC (ABDACB) Suitable for Stereo Audio
Security Features
• One Advanced Encryption System (AES) with 128-bit key length
• 32-bit Cyclic Redundancy Check Calculation Unit (CRCCU)
• Random generator (TRNG)
Debugger Development Support
• Serial Wire/JTAG Debug Port(SWJ-DP)
• Debug access to all memories and registers in the system, including Cortex-M4 register bank when the core is running, halted, or held in reset.
• Serial Wire Debug Port (SW-DP) and Serial Wire JTAG Debug Port (SWJ-DP) debug access.
• Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and code patches.
• Data Watchpoint and Trace (DWT) unit for implementing watchpoints, data tracing, and system profiling.
• Instrumentation Trace Macrocell (ITM) for support of printf style debugging.
• IEEE1149.1 JTAG Boundary-scan on all digital pins.
Integrated Software Libraries and Tools
• ASF-Atmel software Framework – SAM software development framework
• Integrated in the Atmel Studio IDE with a graphical user interface or available as standalone for GCC, IAR compilers.
• DMA support, Interrupt handlers Driver support
• USB, TCP/IP, Wi-Fi and Bluetooth, Numerous USB classes, DHCP and Wi-Fi encryption Stacks
• RTOS integration, FreeRTOS is a core component