ATF1516SE中文资料爱特梅尔数据手册PDF规格书

General Description

Beginning with the introduction of the 100 connected ATF1500 with 32 enhanced macrocells in 1996, Atmel’s CPLD products have delivered extra IO connectivity and logic reusability. Atmel’s commitment to efficient, flexible architecture has continued with the current Atmel ATF15xxSE Family of industry-standard, pin-compatible CPLDs. Atmel’s Logic Doubling architecture consists of wider fan-in, additional routing and clock options, combined with sophisticated, proprietary device fitters, extend CPLD place and route efficiency. Atmel enhanced macrocell includes double independent buried feedback that allows designers to pack more logic (particularly shifters and latches) into a smaller CPLD or leave spare room for later revisions. The Atmel ATF15xxSE family delivers enhanced functionality and flexibility with no additional design effort and is highly cost effective.

特性 Features

• 2nd Generation EE PROM-based Complex Programmable Logic Devices

– VCCIO of 5.0V or 3.3V with 3.3V Operation being 5V Tolerant

– 32 - 256 Macrocells with Enhanced Features

– Pin-compatible with Industry Standard Devices

– Speeds to 5 ns Maximum Pin-to-pin Delay

– Registered Operation to 250 MHz

• Enhanced Macrocells with Logic Doubling™ Features

– Bury Either Register or COM while Using the Other for Output

– Dual Independent Feedback Allows Multiple Latch Functions per Macrocell

– 5 Product Terms per Macrocell, expandable to 40 per Macrocell with Cascade Logic, Plus 15 more with Foldback Logic

– D/T/Latch Configurable Flip-flops plus Transparent Latches

– Global and/or per Macrocell Register Control Signals

– Global and/or per Macrocell Output Enable

– Programmable Output Slew Rate per Macrocell

– Programmable Output Open Collector Option per Macrocell

– Fast Registered Input from Product Term

• Enhanced Connectivity

– Single Level Switch Matrix for Maximum Routing Options

– Up to 40 Inputs per Logic Block

• Advanced Power Management Features

– ITD (Input Transition Detection) Available Individually on Global Clocks, Inputs and I/O for µA Level Standby Current for “L” Versions

– Pin-controlled 1 mA Standby Mode

– Reduced-power Option per Macrocell

– Automatic Power Down of Unused Macrocells

– Programmable Pin-keeper Inputs and I/Os

• Available in Commercial and Industrial Temperature Ranges

• Available in All Popular Packages Including PLCC, PQFP and TQFP

• EE PROM Technology

– 100 Tested

– Completely Reprogrammable

– 10,000 Program/Erase Cycles

– 20 Year Data Retention

– 2000V ESD Protection

– 200 mA Latch-up Immunity

• JTAG Boundary-scan Testing Port per IEEE 1149.1-1990 and 1149.1a-1993

– Pull-up Option on JTAG Pins TMS and TDI

• IEEE 1532 Compatibility for Fast In-System Programmability (ISP) via JTAG

• PCI-compliant

• Security Fuse Feature