AT89C51CC03C-RDTIM中文资料爱特梅尔数据手册PDF规格书

描述 Description

The AT89C51CC03 is a member of the family of 8-bit microcontrollers dedicated to CAN network applications.

In X2 mode a maximum external clock rate of 20 MHz reaches a 300 ns cycle time.

Besides the full CAN controller AT89C51CC03 provides 64K Bytes of Flash memory including In-System Programming (ISP), 2K Bytes Boot Flash Memory, 2K Bytes EEPROM and 2048 byte ERAM.

Primary attention is paid to the reduction of the electro-magnetic emission of AT89C51CC03.

特性 Features

• 80C51 Core Architecture

• 256 Bytes of On-chip RAM

• 2048 Bytes of On-chip ERAM

• 64K Bytes of On-chip Flash Memory

– Data Retention: 10 Years at 85°C

– Read/Write Cycle: 100K

• 2K Bytes of On-chip Flash for Bootloader

• 2K Bytes of On-chip EEPROM

Read/Write Cycle: 100K

• Integrated Power Monitor (POR: PFD) To Supervise Internal Power Supply

• 14-sources 4-level Interrupts

• Three 16-bit Timers/Counters

• Full Duplex UART Compatible 80C51

• High-speed Architecture

– In Standard Mode:

40 MHz (Vcc 3V to 5.5V, both Internal and external code execution)

60 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)

– In X2 mode (6 Clocks/machine cycle)

20 MHz (Vcc 3V to 5.5V, both Internal and external code execution)

30 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)

• Five Ports: 32 + 4 Digital I/O Lines

• Five-channel 16-bit PCA with

– PWM (8-bit)

– High-speed Output

– Timer and Edge Capture

• Double Data Pointer

• 21-bit WatchDog Timer (7 Programmable Bits)

• A 10-bit Resolution Analog to Digital Converter (ADC) with 8 Multiplexed Inputs

• SPI Interface, (PLCC52, VPFP64 and CABGA 64 packages only)

• Full CAN Controller

– Fully Compliant with CAN Rev 2.0A and 2.0B

– Optimized Structure for Communication Management (Via SFR)

– 15 Independent Message Objects

– Each Message Object Programmable on Transmission or Reception

– Individual Tag and Mask Filters up to 29-bit Identifier/Channel

– 8-byte Cyclic Data Register (FIFO)/Message Object

– 16-bit Status and Control Register/Message Object

– 16-bit Time-Stamping Register/Message Object

– CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message Object

– Access to Message Object Control and Data Registers Via SFR

– Programmable Reception Buffer Length Up To 15 Message Objects

– Priority Management of Reception of Hits on Several Message Objects at the Same Time (Basic CAN Feature)

– Priority Management for Transmission

– Message Object Overrun Interrupt

– Supports

– Time Triggered Communication

– Autobaud and Listening Mode

– Programmable Automatic Reply Mode

– 1-Mbit/s Maximum Transfer Rate at 8 MHz (1) Crystal Frequency in X2 Mode

– Readable Error Counters

– Programmable Link to On-chip Timer for Time Stamping and Network Synchronization

– Independent Baud Rate Prescaler

– Data, Remote, Error and Overload Frame Handling

• On-chip Emulation Logic (Enhanced Hook System)

• Power Saving Modes

– Idle Mode

– Power-down Mode

• Power Supply: 3 volts to 5.5 volts

• Temperature Range: Industrial (-40° to +85°C), Automotive (-40°C to +125°C)

• Packages: VQFP44, PLCC44, VQFP64, PLCC52, CA-BGA64