AT25DN512C集成电路（IC）的存储器规格书PDF中文资料

特性 Features

 Single 2.3V - 3.6V Supply

 Serial Peripheral Interface (SPI) Compatible

 Supports SPI Modes 0 and 3

 Supports Dual Output Read

 104MHz Maximum Operating Frequency

 Clock-to-Output (tV) of 6ns

 Flexible, Optimized Erase Architecture for Code + Data Storage Applications

 Small (256-Byte) Page Erase

 Uniform 4-Kbyte Block Erase

 Uniform 32-Kbyte Block Erase

 Full Chip Erase

 Hardware Controlled Locking of Protected Sectors via WP Pin

 128-Byte Programmable OTP Security Register

 64 bytes factory programmed with a unique identifier

 64 bytes user programmable

 Flexible Programming

 Byte/Page Program (1 to 256 Bytes)

 Fast Program and Erase Times

 1.25ms Typical Page Program (256 Bytes) Time

 35ms Typical 4-Kbyte Block Erase Time

 250ms Typical 32-Kbyte Block Erase Time

 Automatic Checking and Reporting of Erase/Program Failures

 Software Controlled Reset

 JEDEC Standard Manufacturer and Device ID Read Methodology

 Low Power Dissipation

 350nA Ultra Deep Power Down current (Typical)

 7.5µA Deep Power-Down Current (Typical)

 25uA Standby current (Typical)

 6mA Active Read Current (Typical)

 Endurance: 100,000 Program/Erase Cycles

 Data Retention: 20 Years

 Complies with Full Industrial Temperature Range

 Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options

 8-lead SOIC (150-mil)

 8-pad Ultra Thin DFN (2 x 3 x 0.6mm)

 8-lead TSSOP Package

描述 Description

The Adesto® AT25DN512C is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer

based applications in which program code is shadowed from Flash memory into embedded or external RAM for execution. The

flexible erase architecture of the AT25DN512C, with its page erase granularity it is ideal for data storage as well, eliminating the

need for additional data storage devices.

The erase block sizes of the AT25DN512C have been optimized to meet the needs of today's code and data storage applications.

By optimizing the size of the erase blocks, the memory space can be used much more efficiently. Because certain code modules

and data storage segments must reside by themselves in their own erase regions, the wasted and unused memory space that

occurs with large sectored and large block erase Flash memory devices can be greatly reduced. This increased memory space

efficiency allows additional code routines and data storage segments to be added while still maintaining the same overall device

density.

The device also contains a specialized OTP (One-Time Programmable) Security Register that can be used for purposes such as

unique device serialization, system-level Electronic Serial Number (ESN) storage, locked key storage, etc.

Specifically designed for use in many different systems, the AT25DN512C supports read, program, and erase operations with a

wide supply voltage range of 2.3V to 3.6V. No separate voltage is required for programming and erasing.