AT24C512W1-10SI-1.8集成电路（IC）的存储器规格书PDF中文资料

Description

The AT24C512 provides 524,288 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 65,536 words of 8 bits each. The device’s cascadable feature allows up to 4 devices to share a common 2-wire bus. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential.

Features

• Low-voltage and Standard-voltage Operation

– 5.0 (VCC= 4.5V to 5.5V)

– 2.7 (VCC= 2.7V to 5.5V)

– 1.8 (VCC= 1.8V to 3.6V)

• Internally Organized 65,536 x 8

• 2-wire Serial Interface

• Schmitt Triggers, Filtered Inputs for Noise Suppression

• Bidirectional Data Transfer Protocol

• 1 MHz (5V), 400 kHz (2.7V) and 100 kHz (1.8V) Compatibility

• Write Protect Pin for Hardware and Software Data Protection

• 128-byte Page Write Mode (Partial Page Writes Allowed)

• Self-timed Write Cycle (5 ms Typical)

• High Reliability

–Endurance: 100,000 Write Cycles

–Data Retention: 40 Years

–ESD Protection: >4000V

• Automotive Grade and Extended Temperature Devices Available

• 8-pin PDIP and 20-pin JEDEC SOIC, 8-pin LAP, and 8-ball dBGATM Packages