AT24C128B集成电路（IC）的存储器规格书PDF中文资料

描述 Description

The AT24C128B provides 131,072 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 16,384 words of 8 bits each. The device’s cascadable feature allows up to eight devices to share a common two-wire bus. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The devices are available in space-saving 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini MAP, 8-lead Ultra Lead Frame Land Grid Array (ULA), 8-lead TSSOP, and 8-ball dBGA2 packages. In addition, the entire family is available in a 1.8V (5.5V to 3.6V) version.

特性 Features

• Low-voltage and Standard-voltage Operation

– 1.8 (VCC = 1.8V to 5.5V)

• Internally Organized as 16,384 x 8

• Two-wire Serial Interface

• Schmitt Trigger, Filtered Inputs for Noise Suppression

• Bidirectional Data Transfer Protocol

• 1 MHz (5.5V, 2.5V), and 400 kHz (1.8V) Compatibility

• Write Protect Pin for Hardware and Software Data Protection

• 64-byte Page Write Mode (Partial Page Writes Allowed)

• Self-timed Write Cycle (5 ms Max)

• High Reliability

– Endurance: One Million Write Cycles

– Data Retention: 40 Years

• Lead-free/Halogen-free

• 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini MAP, 8-lead Ultra Lead

Frame Land Grid Array (ULA), 8-lead TSSOP, and 8-ball dBGA2 Packages

• Die Sales: Wafer Form, Tape and Reel and Bumped Wafers