AT17LV010-10DP中文资料爱特梅尔数据手册PDF规格书

描述 Description

The AT17LV010-10DP is a FPGA Configuration Serial EEPROM provides an easy-to use, cost-effective configuration memory for Field Programmable Gate Arrays. It is packaged in the 28-pin 400 mils wide FP package. Configurator uses a simple serial access procedure to configure one or more FPGA devices. The user can select the polarity of the reset function by programming four EEPROM bytes. The device also supports a write-protection mechanism within its programming mode.

特性 Features

• EE Programmable 1,048,576 x 1-bit Serial Memory Designed to Store Configuration

Programs for Field Programmable Gate Arrays (FPGAs)

• Very Low-power CMOS EEPROM Process

• In-System Programmable (ISP) via Two-Wire Bus

• Simple Interface to SRAM FPGAs

• Compatible with AT40K Devices

• Cascadable Read-back to Support Additional Configurations or Higher-density Arrays

• Programmable Reset Polarity

• Low-power Standby Mode

• High-reliability

– Endurance: 5,104 Read Cycles

– Data Retention: 10 Years

• No Single Event Latch-up below a LET Threshold of 80 MeV/mg/cm2

• Tested up to a Total Dose of (according to MIL STD 883 Method 1019)

– 20 krads (Si) Read-only mode when Biased

– 60 krads (Si) Read-only mode when Unbiased

• Operating Range: 3.0V to 3.6V, -55°C to +125°C

• Available in 400 mils Wide 28 Pins DIL Flat Pack