AS4C256K16F0-50JI中文资料ALSC数据手册PDF规格书

Functional description

The AS4C256K16FO is a high-performance 4 megabit CMOS Dynamic Random Access Memory (DRAM) device organized as 262,144 words × 16 bits. The AS4C256K16FO is fabricated with advanced CMOS technology and designed with innovative design techniques resulting in high speed, extremely low power and wide operating margins at component and system levels.

Features

• Organization: 262,144 words × 16 bits

• High speed

- 25/30/35/50 ns RAS access time

- 12/16/18/25 ns column address access time

- 7/10/10/10 ns CAS access time

• Low power consumption

- Active: 770 mW max (ASAS4C256K16FO-50)

- Standby: 5.5 mW max, CMOS I/O

• Fast page mode

• AS4C256K16FO-50 timings are also valid for AS4C256K16FO-60.

• Refresh

- 512 refresh cycles, 8 ms refresh interval

- RAS-only or CAS-before-RAS refresh or self-refresh

- Self-refresh option is available for new generation device only. Contact Alliance for more information.

• Read-modify-write

• TTL-compatible, three-state I/O

• JEDEC standard packages

- 400 mil, 40-pin SOJ

- 400 mil, 40/44-pin TSOP II

• Single 5V power supply/built-in Vbb generator

• Latch-up current > 200 mA