APR405SLASHD中文资料恩智浦数据手册PDF规格书

FEATURES

Digital Signal Processing Core

• Efficient, object code compatible, 24-bit 56000 family DSP engine

• Up to 16.5 Million Instructions Per Second (MIPS)—60.6 ns instruction cycle at 33 MHz

• Up to 99 Million Operations Per Second (MOPS) at 33 MHz

• Executes a 1024-point complex Fast Fourier Transform (FFT) in 59,898 clocks

• Highly parallel instruction set with unique DSP addressing modes

• Two 56-bit accumulators including extension byte

• Parallel 24x24-bit multiply-accumulate in 1 instruction cycle (2 clock cycles)

• Double precision 48x48-bit multiply with 96-bit result in 6 instruction cycles

• 56-bit addition/subtraction in 1 instruction cycle

• Fractional arithmetic with support for multiprecision arithmetic

• Hardware support for block-floating point FFT

• Hardware nested DO loops

• Zero-overhead fast interrupts (2 instruction cycles)

• Four 24-bit internal data buses and three 16-bit internal address buses for maximum

information transfer on-chip

Memory

• On-chip modified Harvard architecture permitting simultaneous accesses to program

and two data memories

• 512x24-bit on-chip Program RAM and 64x24-bit bootstrap ROM

• Two 256x24-bit on-chip data RAMs

• Two 256x24-bit on-chip data ROMs containing sine, A-law and

u-law tables

• External memory expansion with 16-bit address and 24-bit data buses

• Bootstrap loading from external data bus or Host Interface