AM62A7-Q1数据手册TI中文资料规格书

描述 Description

AM62Ax 是 Sitara™ 汽车级异构 Arm® 处理器系列的扩展，具有嵌入式深度学习(DL)、视频和视觉处理加速、显示接口及广泛的汽车外设和网络选项。AM62Ax 专为一系列成本敏感型汽车应用（包括驾驶员和车内监控系统与下一代电子后视镜系统）以及工厂自动化、楼宇自动化、机器人和其他市场中的广泛工业应用而构建。AM62Ax 对成本进行了优化，能够以业界卓越的功耗/性能比为传统和深度学习算法提供高性能计算，并具有很高的系统集成度，从而使支持独立电子控制单元 (ECU) 中多种传感器模式的高级汽车平台实现可扩展性和更低的成本。

AM62Ax 包含多达四个具有 64 位架构的 Arm® Cortex®-A53 内核、一个具有图像信号处理器 (ISP) 和多个视觉辅助加速器的视觉处理加速器 (VPAC)、多个深度学习 (DL) 和视频加速器、一个 Cortex®-R5F MCU 通道内核以及一个 Cortex®-R5F 器件管理内核。Cortex-A53 提供了 Linux 应用所需的强大计算元件，以及驾驶员监控等基于视觉计算的传统算法的实现。TI 的第七代 ISP 以现有出色的 ISP 为基础，能够灵活地处理更广泛的传感器套件（包括 RGB-IR），支持更高的位深度，并且具有面向分析应用的特性。关键内核包括德州仪器 (TI) 具有标量和矢量内核的下一代 C7000™ DSP (C7x)，以及专用 MMA 深度学习加速器，该加速器在典型的汽车最坏情况结温 125°C 下运行时，可在业界超低的功耗范围内实现高达 2TOPS 的性能。

3 端口千兆位以太网交换机具有一个内部端口和两个支持 TSN 的外部端口，可用于启用工业网络选项。此外，AM62Ax 中随附广泛的外设集，可实现 USB、MMC/SD、摄像头接口、OSPI、CAN-FD 和 GPMC 等系统级连接，用于将主机接口并行连接到外部 ASIC/FPGA。AM62Ax 通过内置 HSM（硬件安全模块）支持安全启动来实现 IP 保护，还为便携式和功耗敏感型应用提供高级电源管理支持。

特性 Features

Processor Cores:
• Up to Quad Arm Cortex-A53 microprocessor subsystem at up to 1.4 GHz
• Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC
• Each A53 core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection

• Single-core Arm Cortex-R5F at up to 800 MHz, integrated as part of MCU Channel with FFI
• 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
• 512KB SRAM with SECDED ECC

• Single-core Arm Cortex-R5F at up to 800 MHz, integrated to support Device Management
• 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories

• Deep Learning Accelerator based on Single-core C7x
• C7x floating point, up to 40 GFLOPS, 256-bit Vector DSP at 1.0 GHz
• Matrix Multiply Accelerator (MMA), up to 2 TOPS (8b) at 1.0 GHz
• 32KB L1 DCache with SECDED ECC and 64KB L1 ICache with Parity protection
• 1.25MB of L2 SRAM with SECDED ECC


• Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators:
• 315 MPixel/s ISP; Up to 5MP @ 60 fps
• Support for 12-bit RGB-IR
• Support for up to 16-bit input RAW format
• Line support up to 4096
• Wide Dynamic Range (WDR), Lens Distortion Correction (LDC), Vision Imaging Subsystem (VISS), and Multi-Scalar (MSC) support
• Output color format : 8-bits, 12-bits, and YUV 4:2:2, YUV 4:2:0, RGB, HSV/HSL


Multimedia:
• Display subsystem
• Single display support
• Up to 2048x1080 @ 60fps
• Up to 165-MHz pixel clock support with independent PLL
• DPI 24-bit RGB parallel interface
• Supports safety features such as freeze frame detection and MISR data check

• One Camera Serial interface (CSI-2) Receiver with 4-Lane D-PHY
• MIPI CSI-2 v1.3 Compliant + MIPI D-PHY 1.2
• Support for 1,2,3 or 4 data lane mode up to 1.5 Gbps per lane
• ECC verification/correction with CRC check + ECC on RAM
• Virtual Channel support (up to 16)
• Ability to write stream data directly to DDR via DMA

• Video Encoder/Decoder
• Support for HEVC (H.265) Main profiles at Level 5.1 High-tier
• Support for H.264 BaseLine/Main/High Profiles at Level 5.2
• Support for up to 4K UHD resolution (3840 × 2160)
• Clocking options supporting 240 MPixels/s, 120 MPixels/s, or 60 MPixels/s


• Motion JPEG encode at 416 MPixels/s with resolutions up to 4K UHD (3840 × 2160)
Memory Subsystem:
• Up to 2.29MB of On-chip RAM
• 64KB of On-Chip RAM (OCRAM) with SECDED ECC, can be divided into smaller banks in increments of 32KB for as many as 2 separate memory banks
• 256KB of On-Chip RAM with SECDED ECC in SMS Subsystem
• 176KB of On-Chip RAM with SECDED ECC in SMS Subsystem for TI security firmware
• 512KB of On-chip RAM with SECDED ECC in Cortex-R5F MCU Subsystem
• 64KB of On-chip RAM with SECDED ECC in Device/Power Manager Subsystem
• 1.25MB of L2 SRAM with SECDED ECC in C7x Deep Learning Accelerator

• DDR Subsystem (DDRSS)
• Supports LPDDR4
• 32-bit data bus with inline ECC
• Supports speeds up to 3733 MT/s
• Max addressable range of 8GBytes

Functional Safety:
• Functional Safety-Compliant targeted [Industrial]
• Developed for functional safety applications
• Documentation will be available to aid IEC 61508 functional safety system design
• Systematic capability up to SIL 3 targeted
• Hardware Integrity up to SIL 2 targeted
• Safety-related certification
• IEC 61508 by TÜV SÜD planned


• Functional Safety-Compliant targeted [Automotive]
• Developed for functional safety applications
• Documentation will be available to aid ISO 26262 functional safety system design
• Systematic capability up to ASIL D targeted
• Hardware integrity up to ASIL B targeted
• Safety-related certification
• ISO 26262 by TÜV SÜD planned


• AEC-Q100 qualified [Automotive]
Security:
• Secure boot supported
• Hardware-enforced Root-of-Trust (RoT)
• Support to switch RoT via backup key
• Support for takeover protection, IP protection, and anti-roll back protection

• Trusted Execution Environment (TEE) supported
• Arm TrustZone based TEE
• Extensive firewall support for isolation
• Secure watchdog/timer/IPC
• Secure storage support
• Replay Protected Memory Block (RPMB) support

• Dedicated Security Controller with user programmable HSM core and dedicated security DMA & IPC subsystem for isolated processing
• Cryptographic acceleration supported
• Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
• Supports cryptographic cores

• AES – 128-/192-/256-Bit key sizes
• SHA2 – 224-/256-/384-/512-Bit key sizes
• DRBG with true random number generator
• PKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure boot

• Debugging security
• Secure software controlled debug access
• Security aware debugging

High-Speed Interfaces:
• Integrated Ethernet switch supporting (total 2 external ports)
• RMII(10/100) or RGMII (10/100/1000)
• IEEE1588 (Annex D, Annex E, Annex F with 802.1AS PTP)
• Clause 45 MDIO PHY management
• Packet Classifier based on ALE engine with 512 classifiers
• Priority based flow control
• Time Sensitive Networking (TSN) support
• Four CPU H/W interrupt Pacing
• IP/UDP/TCP checksum offload in hardware

• Two USB2.0 Ports
• Port configurable as USB host, USB peripheral, or USB Dual-Role Device (DRD mode)
• Integrated USB VBUS detection

General Connectivity:
• 9x Universal Asynchronous Receiver-Transmitters (UART)
• 5x Serial Peripheral Interface (SPI) controllers
• 6x Inter-Integrated Circuit (I2C) ports
• 3x Multichannel Audio Serial Ports (McASP)
• Transmit and Receive Clocks up to 50 MHz
• Up to 16/10/6 Serial Data Pins across 3x McASP with Independent TX and RX Clocks
• Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
• Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
• FIFO Buffers for Transmit and Receive (256 Bytes)
• Support for audio reference output clock

• 3x enhanced PWM modules (ePWM)
• 3x enhanced Quadrature Encoder Pulse modules (eQEP)
• 3x enhanced Capture modules (eCAP)
• General-Purpose I/O (GPIO), All LVCMOS I/O can be configured as GPIO
• 3x Controller Area Network (CAN) modules with CAN-FD support
• Conforms w/ CAN Protocol 2.0 A, B and ISO 11898-1
• Full CAN FD support (up to 64 data bytes)
• Parity/ECC check for Message RAM
• Speed up to 8 Mbps

Media and Data Storage:
• 3x Secure Digital (SD) (4b+4b+8b) interface
• 1x 8-bit eMMC interface up to HS200 speed
• 2x 4-bit SD/SDIO interface up to UHS-I
• Compliant with eMMC 5.1, SD 3.0, and SDIO Version 3.0

• 1× General-Purpose Memory Controller (GPMC) up to 133 MHz
• Flexible 8- and 16-bit Asynchronous Memory Interface with up to four Chip (22-bit address) Selects (NAND, NOR, Muxed-NOR, and SRAM)
• Uses BCH code to support 4-, 8-, or 16-bit ECC
• Uses Hamming code to support 1-bit ECC
• Error Locator Module (ELM)
• Used with the GPMC to locate addresses of data errors from syndrome polynomials generated using a BCH algorithm
• Supports 4-, 8-, and 16-bit per 512-Byte block error location based on BCH algorithms


• OSPI/QSPI with DDR / SDR support
• Support for Serial NAND and Serial NOR Flash devices
• 4GBytes memory address support
• XIP mode with optional on-the-fly encryption

Power Management:
• Low-power modes supported by Device/Power Manager
• Partial IO support for CAN/GPIO/UART wakeup
• DeepSleep : I/O + DDR (suspend to RAM)
• DeepSleep
• MCU Only
• Standby
• Dynamic frequency scaling for Cortex-A53

Boot Options:
• UART
• I2C EEPROM
• OSPI/QSPI Flash
• GPMC NOR/NAND Flash
• SD Card
• eMMC
• USB (host) Mass storage
• USB (device) boot from external host (DFU mode)
• Ethernet
Technology / Package:
• 16-nm FinFET technology
• 18 mm x 18 mm, 0.8-mm pitch full-array, 484-pin FCBGA (AMB)