AM625中文资料具有基于 Arm® Cortex®-A53 的边缘 AI 和全高清双显示的人机交互 SoC数据手册TI规格书

特性 Features

Processor Cores:
• Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC
• Single-core Arm® Cortex®-M4F MCU at up to 400 MHz
• Dedicated Device and Power Manager
• Display subsystem
• 1920x1080 @ 60fps for each display
• Up to 200-MHz pixel clock support with Independent PLL for each display
• Support safety feature such as freeze frame detection and MISR data check
• 3D Graphics Processing Unit
• Fillrate greater than 500 Mpixels/sec
• Supports at least 2 composition layers
• Supports ARGB32, RGB565 and YUV formats
• OpenGL 3.x/2.0/1.1 + Extensions, Vulkan 1.2
• One Camera Serial interface (CSI-Rx) - 4 Lane with DPHY
• Support for 1,2,3 or 4 data lane mode up to 2.5Gbps
• Virtual Channel support (up to 16)
• Up to 816KB of On-chip RAM
• 256KB of On-chip RAM with SECDED ECC in SMS Subsystem
• 256KB of On-chip RAM with SECDED ECC in Cortex-M4F MCU subsystem
• DDR Subsystem (DDRSS)
• 16-Bit data bus with inline ECC
• Max addressable range
• 4GBytes with LPDDR4
• Functional Safety-Compliant targeted [Industrial]
• Documentation will be available to aid IEC 61508 functional safety system design
• Hardware Integrity up to SIL 2 targeted
• IEC 61508 by TUV SUD planned
• Functional Safety-Compliant targeted [Automotive]
• Documentation will be available to aid ISO 26262 functional safety system design
• Hardware integrity up to ASIL B targeted
• ISO 26262 by TUV SUD planned
• AEC-Q100 qualified
• Hardware Security Module
• Dedicated security DMA and IPC subsystem for isolated processing
• Secure boot supported
• Support to switch RoT via backup key
• Cryptographic acceleration supported
• Supports cryptographic cores
• SHA2 – 224/256/384/512
• PKA (Public Key Accelerator) to Assist in RSA/ECC processing
• DMA support
• Debugging security
• Security aware debugging
• Trusted Execution Environment (TEE) supported
• Extensive firewall support for isolation
• Secure storage support
• Dual-core Programmable Real-Time Unit running up to 333 MHz and Industrial Communication Subystem (PRU-ICSS)
• General Purpose Input/Output (GPIO)
• I2C
• 16KByte program memory per PRU with SECDED ECC
• 32KB general purpose memory with SECDED ECC
• Scratch PAD memory with 3 banks of 30 x 32-bit registers
• 1 interrupt controller (INTC), minimum of 64 input events supported
• Integrated Ethernet switch supporting (total 2 external ports)
• IEEE1588 (Annex D, Annex E, Annex F with 802.1AS PTP)
• Packet Classifier based on ALE engine with 512 classifiers
• Time sensitive networking (TSN) support
• IP/UDP/TCP checksum offload in hardware
• Two USB2.0 Ports
• Integrated USB VBUS detection
• 9x Universal Asynchronous Receiver-Transmitters (UART)
• 6x Inter-Integrated Circuit (I2C) ports
• Transmit and Receive Clocks up to 50 MHz
• Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
• FIFO Buffers for Transmit and Receive (256 Bytes)
• 3x enhanced PWM modules (ePWM)
• 3x enhanced Capture modules (eCAP)
• 3x Controller Area Network (CAN) modules with CAN-FD support
• Full CAN FD support (up to 64 data bytes)
• Speed up to 8Mbps
• 3x Secure Digital (SD) (4b+4b+8b) interface
• 2x 4-bit SD/SDIO interface up to UHS-I
• 1× General-Purpose Memory Controller (GPMC) up to 133 MHz
• Uses BCH Code to Support 4-, 8-, or 16-Bit ECC
• Error Locator Module (ELM)
• Supports 4-, 8-, and 16-Bit Per 512-Byte Block Error Location Based on BCH Algorithms
• OSPI/QSPI with 166-MHz DDR / 200-MHz SDR
• Up to 4 CS supported
• XIP mode with optional on-the-fly encryption
• Low power modes supported by Device Manager
• DeepSleep
• Standby
• Recommended TPS65219 Power Management ICs (PMIC)
• Flexible mapping and factory programmed configurations to support different use cases
• UART
• OSPI/QSPI Flash
• Serial NAND Flash
• eMMC
• USB (device) boot from external host (DFU mode)
• 16-nm technology
• 17.2 mm x 17.2 mm, 0.8-mm pitch, 441-pin FCBGA (AMC)