GENERAL DESCRIPTION

The High Performance SCSI Controller (HPSC) has a flexible three bus architecture. The HPSC has a 16-bit DMA interface, an 8 bit host data interface and an 8-bit SCSI data interface. The HPSC is designed to minimize host intervention by implementing common SCSI sequences in hardware. An on-chip state machine reduces protocol overheads by performing the required sequences in response to a single command from the host. Selection, reselection, information transfer and disconnection commands are directly supported.

DISTINCTIVE CHARACTERISTICS

■ Pin/function compatible with NCR53C94/53C96

■ AMD’s Patented GLITCH EATERTM Circuitry on REQ and ACK inputs

■ 5 Mbytes per second synchronous SCSI transfer rate

■ 20 Mbytes per second DMA transfer rate

■ 16-bit DMA Interface plus 2 bits of parity

■ Flexible three bus architecture

■ Single ended SCSI bus supported by Am53C94

■ Single ended and differential SCSI bus supported by Am53C96

■ Selection of multiplexed or non-multiplexed address and data bus

■ High current drivers (48 mA) for direct connection to the single ended SCSI bus

■ Supports Disconnect and Reselect commands

■ Supports burst mode DMA operation with a threshold of 8

■ Supports 3-byte-tagged queuing as per the SCSI-2 specification

■ Supports group 2 and 5 command recognition as per the SCSI-2 specification

■ Advanced CMOS process for low power consumption

■ Am53C94 available in 84-pin PLCC package

■ Am53C96 available in 100-pin PQFP package