AM2612中文资料Dual-core Arm Cortex-R5F MCU up to 400 MHz with real-time control and security数据手册TI规格书

描述 Description

The AM261x Sitara Arm Microcontrollers are part of Sitara AM26x real-time MCU families designed to meet the complex real-time processing needs of next generation industrial and automotive embedded products. With scalable Arm Cortex R5F performance and an extensive set of peripherals, AM261x device is designed for a broad range of applications while offering safety features and optimized peripherals for real time control.

Key features and benefits:

Peripherals supporting system level connectivity such as Gigabit Ethernet, USB, OSPI/QSPI, CAN, UARTs, SPI and GPIOs. Granular firewalls managed by Hardware Security Manager (HSM) enable developers to implement stringent security minded system design requirements. Up to two R5F cores in cluster with 256KB of shared Tightly Coupled Memory (TCM) per core along with 1.5MB of shared SRAM, greatly reducing the need for external memory.

The AM261x Sitara Arm Microcontrollers are part of Sitara AM26x real-time MCU families designed to meet the complex real-time processing needs of next generation industrial and automotive embedded products. With scalable Arm Cortex R5F performance and an extensive set of peripherals, AM261x device is designed for a broad range of applications while offering safety features and optimized peripherals for real time control.

Key features and benefits:

Peripherals supporting system level connectivity such as Gigabit Ethernet, USB, OSPI/QSPI, CAN, UARTs, SPI and GPIOs. Granular firewalls managed by Hardware Security Manager (HSM) enable developers to implement stringent security minded system design requirements. Up to two R5F cores in cluster with 256KB of shared Tightly Coupled Memory (TCM) per core along with 1.5MB of shared SRAM, greatly reducing the need for external memory.

特性 Features

• Single and Dual Arm Cortex R5F CPU with each core running up to 500 MHz
• 16KB D-cache with 32-bit ECC per CPU core
• Lockstep or Dual core operation supported
• Trigonometric Math Unit (TMU) for accelerating trigonometric functions
• 1.5MB of On-Chip Shared SRAM (3 banks × 512KB). ECC error protection for full 1.5MB OCSRAM.
• 1 × EDMA to support data movement functions
• UART (Primary/Backup)
• USB Peripheral boot
• Interprocessor communication modules
• MAILBOX functionality implemented through CTRLMMR registers
• 2 × Octal Serial Peripheral Interface (OSPI) at up to 133-MHz SDR and 133-MHz DDR at 1.8V and 3.3V which can be used for
• RAM expansion/FOTA
• 1 × 4-bit Multi-Media Card/Secure Digital (MMC/SD) interface
• 16-bit parallel data bus with 22-bit address bus and 4 chip selects
• Integrated Error Location Module (ELM) support for error checking
• 6 × Universal Asynchronous RX-TX (UART) modules
• 3 × Local Interconnect Network (LIN) ports
• 2 × Modular Controller Area Network (MCAN) modules with CAN-FD support
• 1 × Fast Serial Interface Receiver (FSIRX) at up to 200Mbps
• Port configurable as USB host, USB device, or USB Dual-Role device
• High-Speed (HS, 480Mbps)
• Low-Speed (LS, 1.5Mbps)
• USB 2.0 Device mode
• Full-Speed (FS, 12Mbps)
• Real-time Control Subsystem (CONTROLSS)
• 3 × 12-bit Analog to Digital Converters (ADC) with 3 MSPS maximum sampling rate
• 7× Single ended channels OR
• Highly configurable ADC digital logic
• 4 × Post-Processing blocks for each ADC module
• 9 × Analog Comparators with internal 12-bit DAC reference (CMPSS-A)
• 10 × Enhanced High Resolution Pulse Width Modulation (eHRPWM) modules
• Advanced PWM Configurations
• 8 × Enhanced Capture (ECAP) modules
• 2 × Sigma-Delta Filter Modules (SDFM)
• 2× Programmable Real-time Unit – Industrial Communication SubSystem(2× PRU-ICSS)
• Dual core Programmable Realtime Unit Subsystem (PRU0 / PRU1)
• Dynamic firmware
• 20-channel enhanced input (eGPI) per PRU
• Embedded Peripherals and Memory
• 1 × MDIO, 1x IEP
• 2 × 8KB Shared Data RAM
• ScratchPad (SPAD), MAC/CRC
• Digital encoder and sigma-delta control loops
• EtherCAT, Ethernet/IP™
• Dedicated Interrupt Controller (INTC)
• Supports standard ethernet (EMAC) – up to 2 external ports
• Integrated Ethernet Switch(CPSW3G)
• IEEE 1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTP
• 512 × ALE engine based packet classifiers
• Four CPU hardware interrupt pacing
• Supports TSN
• Hardware Security Module (HSM) with support for Auto SHE 1.1/EVITA
• Secure boot support
• Hardware enforced root-of-trust
• SW Anti-rollback protection
• Debug security
• Ability to disable device debug functionality
• Device ID and Key Management
• Store root keys and other security fields
• Separate EFUSE controllers and FUSE ROMs
• Memory Protection Units (MPU)
• System MPU - present at various interfaces in the SoC (MPU or Firewall)
• Enable/Privilege ID
• Read/Write/Cachable
• Cryptographic acceleration
• AES - 128/192/256-bit key sizes
• DRBG with pseudo and true random number generator
• Enables design of systems with functional safety requirements
• ECC or parity on calculation critical memories
• Runtime internal diagnostic modules including voltage, temperature, and clock monitoring, windowed watchdog timers, CRC engines for memory integrity checks
• Functional Safety-Compliant targeted [Industrial]
• Documentation to be made available to aid IEC 61508 functional safety system design
• Hardware integrity up to SIL-3 targeted
• IEC 61508 planned
• Functional Safety-Compliant targeted [Automotive]
• Documentation to be made available to aid ISO 26262 functional safety system design
• Hardware integrity up to ASIL-D targeted
• ISO 26262 planned
• AEC-Q100 qualified for automotive applications
• Available multiple NFBGA packages (see Section 3)
• With 0.5mm, 0.65 mm and 0.8 mm pitch options