丝印：AM2612ALDFHMZCZQ1508；Package：NFBGA(ZCZ)；AM261x Sitara™ Microcontrollers

1 Features Processor Cores: • Single and Dual Arm® Cortex® R5F CPU with each core running up to 500MHz – 16KB I-Cache with 64-bit ECC per CPU core – 16KB D-cache with 32-bit ECC per CPU core – 256KB Tightly Coupled Memory (TCM) with 32- bit ECC per core – Lockstep or Dual-core operation su

文件：6.94604 Mbytes 页数：214 Pages

TI

德州仪器

丝印：AM2612AOFFHIZFG508；Package：NFBGA(ZFG)；AM261x Sitara™ Microcontrollers

1 Features Processor Cores: • Single and Dual Arm® Cortex® R5F CPU with each core running up to 500MHz – 16KB I-Cache with 64-bit ECC per CPU core – 16KB D-cache with 32-bit ECC per CPU core – 256KB Tightly Coupled Memory (TCM) with 32- bit ECC per core – Lockstep or Dual-core operation su

文件：6.94604 Mbytes 页数：214 Pages

TI

德州仪器

AM261x Sitara™ Microcontrollers

1 Features Processor Cores: • Single and Dual Arm® Cortex® R5F CPU with each core running up to 500MHz – 16KB I-Cache with 64-bit ECC per CPU core – 16KB D-cache with 32-bit ECC per CPU core – 256KB Tightly Coupled Memory (TCM) with 32- bit ECC per core – Lockstep or Dual-core operation su

文件：6.95231 Mbytes 页数：214 Pages

TI

德州仪器

AM261x Sitara™ Microcontrollers

1 Features Processor Cores: • Single and Dual Arm® Cortex® R5F CPU with each core running up to 500MHz – 16KB I-Cache with 64-bit ECC per CPU core – 16KB D-cache with 32-bit ECC per CPU core – 256KB Tightly Coupled Memory (TCM) with 32- bit ECC per core – Lockstep or Dual-core operation su

文件：6.95231 Mbytes 页数：214 Pages

TI

德州仪器

AM261x Sitara™ Microcontrollers

1 Features Processor Cores: • Single and Dual Arm® Cortex® R5F CPU with each core running up to 500MHz – 16KB I-Cache with 64-bit ECC per CPU core – 16KB D-cache with 32-bit ECC per CPU core – 256KB Tightly Coupled Memory (TCM) with 32- bit ECC per core – Lockstep or Dual-core operation su

文件：6.95231 Mbytes 页数：214 Pages

TI

德州仪器

AM261x Sitara™ Microcontrollers

1 Features Processor Cores: • Single and Dual Arm® Cortex® R5F CPU with each core running up to 500MHz – 16KB I-Cache with 64-bit ECC per CPU core – 16KB D-cache with 32-bit ECC per CPU core – 256KB Tightly Coupled Memory (TCM) with 32- bit ECC per core – Lockstep or Dual-core operation su

文件：6.94604 Mbytes 页数：214 Pages

TI

德州仪器

Quad RS-232C Line Receiver

Quad RS-232C Line Receiver

文件：192.45 Kbytes 页数：4 Pages

AMD

超威半导体

Quad RS-232C Line Receiver

Quad RS-232C Line Receiver

文件：192.45 Kbytes 页数：4 Pages

AMD

超威半导体

Quad RS-232C Line Receiver

Quad RS-232C Line Receiver

文件：192.45 Kbytes 页数：4 Pages

AMD

超威半导体

Quad RS-232C Line Receiver

Quad RS-232C Line Receiver

文件：192.45 Kbytes 页数：4 Pages

AMD

超威半导体