AM1806中文资料Sitara 处理器：Arm9，LPDDR，DDR2，显示数据手册TI规格书

描述 Description

The AM1806 ARM Microprocessor is a low-power applications processor based on ARM926EJ-S. The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution. The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously. The ARM core has a coprocessor 15 (CP15), protection module, and data and program memory management units (MMUs) with table look-aside buffers. The ARM core processor has separate 16-KB instruction and 16-KB data caches. Both are four-way associative with virtual index virtual tag (VIVT). The ARM core also has 8KB of RAM (Vector Table) and 64KB of ROM. The peripheral set includes: one USB2.0 OTG interface; two inter-integrated circuit (I2C Bus) interfaces; one multichannel audio serial port (McASP) with 16 serializers and FIFO buffers; two multichannel buffered serial ports (McBSPs) with FIFO buffers; two serial peripheral interfaces (SPIs) with multiple chip selects; four 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host-port interface (HPI); up to 9 banks of general-purpose input/output (GPIO) pins, with each bank containing 16 pins with programmable interrupt and event generation modes, multiplexed with other peripherals; three UART interfaces (each with RTS and CTS); two enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two external memory interfaces; an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals; and a higher speed DDR2/Mobile DDR controller. The universal parallel port (uPP) provides a high-speed interface to many types of data converters, FPGAs or other parallel devices. The uPP supports programmable data widths between 8- to 16-bits on both channels. Single-data rate and double-data rate transfers are supported as well as START, ENABLE, and WAIT signals to provide control for a variety of data converters. A video port interface (VPIF) is included providing a flexible video I/O port. The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections in this document and the associated peripheral reference guides.The device has a complete set of development tools for the ARM processor. These tools include C compilers, and scheduling, and a Windows debugger interface for visibility into source code execution.

特性 Features

• 375- and 456-MHz ARM926EJ-S RISC MPU
• 2 Channel Controllers
• 64 Independent DMA Channels
• Programmable Transfer Burst Size
• 1.8-V or 3.3-V LVCMOS I/Os (Except for USB and DDR2 Interfaces)
• EMIFA
• NAND (8- or 16-Bit-Wide Data)
• DDR2/Mobile DDR Memory Controller with one of the following:
• 16-Bit mDDR SDRAM with 256-MB Address Space
• Three Configurable 16550-Type UART Modules:
• 16-Byte FIFO
• LCD Controller
• Two Multimedia Card (MMC)/Secure Digital (SD) Card Interfaces with Secure Data I/O (SDIO) Interfaces
• One Host-Port Interface (HPI) with 16-Bit-Wide Muxed Address and Data Bus For High Bandwidth
• Two Independent Programmable Real-Time Unit (PRU) Cores
• 4KB of Instruction RAM per Core
• PRUSS can be Disabled via Software to Save Power
• Standard Power-Management Mechanism
• Entire Subsystem Under a Single PSC Clock Gating Domain
• Dedicated Interrupt Controller
• USB 2.0 OTG Port with Integrated PHY (USB0)
• USB 2.0 High-, Full-, and Low-Speed Host
• End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) RX and TX
• One Multichannel Audio Serial Port (McASP):
• Two Clock Zones and 16 Serial Data Pins
• DIT-Capable
• Two Multichannel Buffered Serial Ports (McBSPs):
• Supports TDM, I2S, and Similar Formats
• Telecom Interfaces (ST-Bus, H100)
• FIFO Buffers for Transmit and Receive
• Video Port Interface (VPIF):
• Two 8-Bit SD (BT.656), Single 16-Bit Video Display Channels
• Universal Parallel Port (uPP):
• Data Width on Both Channels is 8- to 16-Bit Inclusive
• Supports Multiple Interfaces with START, ENABLE, and WAIT Controls
• Real-Time Clock (RTC) with 32-kHz Oscillator and Separate Power Rail
• One 64-Bit General-Purpose or Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
• Dedicated 16-Bit Time-Base Counter with Period and Frequency Control
• Dead-Band Generation
• Trip Zone Input
• Three 32-Bit Enhanced Capture (eCAP) Modules:
• Single-Shot Capture of up to Four Event Time-Stamps
• 361-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZCE Suffix], 0.65-mm Ball Pitch
• Commercial or Extended Temperature