AM1707中文资料Sitara 处理器：Arm9，SDRAM，以太网，显示数据手册TI规格书

描述 Description

The device is a low-power ARM microprocessor based on an ARM926EJ-S. The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution. The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously. The ARM core has a coprocessor 15 (CP15), protection module, and data and program memory management units (MMUs) with table look-aside buffers. The ARM core has separate 16KB of instruction and 16-KB data caches. Both memory blocks are four-way associative with virtual index virtual tag (VIVT). The ARM core also has 8KB of RAM (Vector Table) and 64KB of ROM. The peripheral set includes: a 10/100 Mbps Ethernet MAC (EMAC) with a management data input/output (MDIO) module; two I2C Bus interfaces; 3 multichannel audio serial port (McASP) with 16/12/4 serializers and FIFO buffers; two 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host-port interface (HPI); up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; three UART interfaces (one with both RTS and CTS); three enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two 32-bit enhanced quadrature encoded pulse (eQEP) peripherals; and 2 external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM. The Ethernet Media Access Controller (EMAC) provides an efficient interface between the device and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration. The HPI, I2C, SPI, USB1.1, and USB2.0 ports allow the device to easily control peripheral devices and/or communicate with host processors.The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.The device has a complete set of development tools for the ARM processor. These include C compilers and a Windows® debugger interface for visibility into source code execution.

特性 Features

• 375- and 456-MHz ARM926EJ-S™ RISC Core
• Single-Cycle MAC
• Embedded ICE-RT™ for Real-Time Debug
• ARM9 Memory Architecture
• 16KB of Data Cache
• 64KB of ROM
• Enhanced Direct Memory Access Controller 3 (EDMA3):
• 32 Independent DMA Channels
• Programmable Transfer Burst Size
• 128KB of RAM Memory
• Two External Memory Interfaces:
• NOR (8- or 16-Bit-Wide Data)
• 16-Bit SDRAM with 128-MB Address Space
• EMIFB
• Three Configurable 16550-Type UART Modules:
• 16-Byte FIFO
• Autoflow Control Signals (CTS, RTS) on UART0 Only
• LCD Controller
• Programmable Real-Time Unit Subsystem (PRUSS)
• 32-Bit Load-Store RISC Architecture
• 512 Bytes of Data RAM per Core
• Standard Power-Management Mechanism
• Entire Subsystem Under a Single PSC Clock Gating Domain
• Dedicated Interrupt Controller
• Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO)
• One Host-Port Interface (HPI) with 16-Bit-Wide Muxed Address/Data Bus for High Bandwidth
• USB 2.0 OTG Port with Integrated PHY (USB0)
• USB 2.0 High-, Full-, and Low-Speed Host
• End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) RX and TX
• Three Multichannel Audio Serial Ports (McASPs):
• Supports TDM, I2S, and Similar Formats
• FIFO Buffers for Transmit and Receive
• 10/100 Mbps Ethernet MAC (EMAC):
• RMII Media-Independent Interface
• Real-Time Clock (RTC) with 32-kHz Oscillator and Separate Power Rail
• One 64-Bit General-Purpose Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
• Dedicated 16-Bit Time-Base Counter with Period and Frequency Control
• Dead-Band Generation
• Trip Zone Input
• Three 32-Bit Enhanced Capture (eCAP) Modules:
• Single-Shot Capture of up to Four Event Time-Stamps
• Two 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
• Commercial, Industrial, Automotive, or Extended Temperature