AKD7782数据手册AKM中文资料规格书

描述 Description

GENERAL DESCRIPTION
The AK7782 is an audio digital signal processor with integrated 24bit 5ch ADCs, an 8:2 stereo input selector and sample rate converters that support 2ch inputs and the frequency up to 96kHz. The ADC supports wide range of sampling frequency from 7.35kHz to 96kHz. Two integrated audio DSPs have high performance processing speed of 2560step/fs (at 48kHz sampling), and two 6k-word delay RAMs allow surround processing, time alignment adjusting and FIR filtering. As the AK7782 is a RAM based DSP, it is programmable for various user requirements. It is housed in a 100pin LQFP package.FEATURES
[DSP1/DSP2]
□ Word Length: 28-bits
□ Instruction Cycle Time: 8.1ns (2560fs, fs=48kHz)
□ Processing Step: 2560 steps (max) /fs= 48kHz, 44.1kHz (Normal Speed)
   15360 steps (max) /fs= 8kHz, 7.35kHz
   1280 steps (max) fs= 96kHz, 88.2kHz (Double Speed)
□ Multiplier: 24 x 16 → 40-bits (double precision available)
□ Divider: 24 ÷ 24 → 24-bits (floating point normalization function)
□ ALU: 44-bit arithmetic operation (with 4-bit overflow margin)
   24-bit arithmetic and logic operation
□ Data Shift: Right shift after multiplication 1, 2, 4, 5, 8, 14, 15-bits
   Right shift BUS 1, 2, 3, 4, 8, 14, 15-bits
   Left shift after multiplication 1, 2, 3, 4, 8, 15-bits
   Left shift BUS 1, 2, 3, 4, 6, 8, 15-bits
   Indirect shifting function
□ Program RAM (PRAM): 2048word x 36-bits
□ Coefficient RAM (CRAM): 2048word x 16-bits
□ Data RAM (DRAM): 2048word x 28-bits
□ Offset Register (OFREG): 64word x 13-bits
□ Delay RAM (DLRAM): 168kbit (four types)
   ● 6kword 28-bits
   ● 4kword 28-bits + 4kword 14-bits
   ● 3kword 28-bits + 6kword 14-bits
   ● 3kword 28-bits + 3kword 28-bits (Linear)
□ Register: 44-bits x 4 (ACC) [for ALU]
   28-bits x 12 (TMP) [DBUS connection]
   28-bits x 6 steps stack (PTMP) [DBUS connection]

特性 Features

[DSP1/DSP2]
□ Word Length: 28-bits
□ Instruction Cycle Time: 8.1ns (2560fs, fs=48kHz)
□ Processing Step: 2560 steps (max) /fs= 48kHz, 44.1kHz (Normal Speed)
   15360 steps (max) /fs= 8kHz, 7.35kHz
   1280 steps (max) fs= 96kHz, 88.2kHz (Double Speed)
□ Multiplier: 24 x 16 → 40-bits (double precision available)
□ Divider: 24 ÷ 24 → 24-bits (floating point normalization function)
□ ALU: 44-bit arithmetic operation (with 4-bit overflow margin)
   24-bit arithmetic and logic operation
□ Data Shift: Right shift after multiplication 1, 2, 4, 5, 8, 14, 15-bits
   Right shift BUS 1, 2, 3, 4, 8, 14, 15-bits
   Left shift after multiplication 1, 2, 3, 4, 8, 15-bits
   Left shift BUS 1, 2, 3, 4, 6, 8, 15-bits
   Indirect shifting function
□ Program RAM (PRAM): 2048word x 36-bits
□ Coefficient RAM (CRAM): 2048word x 16-bits
□ Data RAM (DRAM): 2048word x 28-bits
□ Offset Register (OFREG): 64word x 13-bits
□ Delay RAM (DLRAM): 168kbit (four types)
   ● 6kword 28-bits
   ● 4kword 28-bits + 4kword 14-bits
   ● 3kword 28-bits + 6kword 14-bits
   ● 3kword 28-bits + 3kword 28-bits (Linear)
□ Register: 44-bits x 4 (ACC) [for ALU]
   28-bits x 12 (TMP) [DBUS connection]
   28-bits x 6 steps stack (PTMP) [DBUS connection]