AiP74HC237中文资料带地址锁存的3-8译码器/信号分离器数据手册I-CORE规格书

描述 Description

The AiP74HC/HCT237 is a 3-to-8 line decoder, demultiplexer with latches at the three address inputs (An). The AiP74HC/HCT237 essentially combines the 3-to-8 decoder function with a 3-bit storage latch. When the latch is enabled (LE(—)=LOW), the AiP74HC/HCT237 acts as a 3-to-8 active LOW decoder. When the latch enable (LE(—)) goes from LOW-to-HIGH, the last data present at the inputs before this transition, is stored in the latches. Further address changes are ignored as long as LE(—) remains HIGH. The output enable input (E(—)1 and E2) controls the state of the outputs independent of the address inputs or latch operation. All outputs are HIGH unless E(—)1 is LOW and E2 is HIGH. The AiP74HC/HCT237 is ideally suited for implementing non-overlapping decoders in 3-state systems and strobes (stored address) applications in bus-oriented systems.

特性 Features

•Input levels:
• For AiP74HC237: CMOS level
• For AiP74HCT237: TTL level
•Combines 3-to-8 decoder with 3-bit latch
•Multiple input enable for easy expansion or independent controls
•Active HIGH mutually exclusive outputs
•Low-power dissipation
•Specified from -40℃ to +125℃
•Packaging information: DIP16/SOP16/TSSOP16

应用 Application

• 家用电器
• 工业控制
• 新能源