AiP74HC138数据手册I-CORE中文资料规格书

描述 Description

The AiP74HC/HCT138 decodes three binary weighted address inputs(A0, A1 and A2) to eight mutually exclusive outputs (Y(—)0 to Y(—)7). The device features three enable inputs (E(—)1, E(—)2 and E3). Every output will be HIGH unless E(—)1 and E(—)2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion to a 1-of-32(5 to 32 lines) decoder with just four AiP74HC/HCT138 ICs and one inverter. The AiP74HC/HCT138 can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

特性 Features

•Input levels:
• For AiP74HC138: CMOS level
• For AiP74HCT138: TTL level
•Demultiplexing capability
•Multiple input enable for easy expansion
•Ideal for memory chip select decoding
•Active LOW mutually exclusive outputs
•Specified from -40℃ to +125℃
•Packaging information: DIP16/SOP16/TSSOP16

应用 Application

• 家用电器
• 工业控制
• 新能源