AiP74AUP1G74数据手册I-CORE中文资料规格书

描述 Description

The AiP74AUP1G74 provides a low-power, low-voltage single positive-edge triggered D-type flip-flop with individual data (D), clock (CP), set ( ) and reset ( ) inputs and complementary Q and outputs. Theandare asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8V to 3.6V.This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8V to 3.6V.This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

特性 Features

• Wide supply voltage range from 0.8V to 3.6V
• Low static power consumption; ICC=1uA (maximum)
• Inputs accept voltages up to 3.6V
• Low noise overshoot and undershoot<10% of VCC
• IOFF circuitry provides partial power-down mode operation
• Multiple package options
• Specified from -40℃ to +125℃
• Packaging information: TSSOP8/VSSOP8

应用 Application

• 家用电器
• 工业控制
• 新能源