AHV85110中文资料ALLEGRO数据手册PDF规格书

FEATURES AND BENEFITS

• Power-Thru integrated isolated bias

□ No high-side bootstrap

□ No external secondary-side bias

• 50 ns propagation delay, with excellent device-to-device

matching of 5 ns

• Separate drive output pins: pull-up (2.8 Ω) and pull-down

(1.0 Ω)

• Supply voltage 10.5 V < VDRV < 13.2 V

• Undervoltage lockout on primary VDRV and secondary VSEC

• Enable pin with fast response

• Continuous ON capability—no need to recycle IN or

recharge bootstrap capacitor

• CMTI > 100 V/ns dv/dt immunity

• Creepage distance > 8 mm

• Distance-through-insulation DTI ≥ 450 μm

• Safety Regulatory Approvals (pending)

□ 5.7 kV RMS VISO per UL 1577

□ 8 kV pk VIOTM maximum transient isolation voltage

per VDE0884-11

□ 630 V pk maximum working isolation voltage

DESCRIPTION

The AHV85110 isolated gate driver is optimized for driving

GaNFETs in multiple applications and topologies. An isolated

output bias supply is integrated into the driver device, eliminating

the need for any external gate drive auxiliary bias supply or

high-side bootstrap. This greatly simplifies the system design

and reduces EMI through reduced total common-mode (CM)

capacitance. It also allows the driving of a floating switch in

any location in a switching power topology.

The driver has fast propagation delay and high peak source/

sink capability to efficiently drive GaNFETs in high-frequency

designs. High CMTI combined with isolated outputs for both

bias power and drive make it ideal in applications requiring

isolation, level-shifting, or ground separation for noise immunity.

The device is available in a compact low-profile surface-mount

NH package. Several protection features are integrated, including

undervoltage lockout on primary and secondary bias rails,

internal pull-down on IN pin and OUTPD pin, fast response

enable input, and OUT pulse synchronization with first IN

rising edge after enable (avoids asynchronous runt pulses).