ADSP-TS101SAB1Z100集成电路（IC）的DSP（数字信号处理器）规格书PDF中文资料

ADSP-TS101SAB1Z100属于集成电路（IC）的DSP（数字信号处理器）。由亚德诺半导体技术有限公司制造生产的ADSP-TS101SAB1Z100DSP（数字信号处理器）数字信号处理器是类似于微处理器或微控制器的器件，但区别在于其内部架构经修改，适用于对连续数据流连续执行以乘法和加法运算为主的算法，而不是以条件逻辑或大量并发进程为主的算法。该器件通常用于诸如音频或视频信号处理等应用。

GENERAL DESCRIPTION

The ADSP-TS101S TigerSHARC® processor is an ultrahigh performance, Static SuperscalarTM †processor optimized for large signal processing tasks and communications infrastructure. The DSP combines very wide memory widths with dual computation blocks—supporting 32- and 40-bit floating-point and 8-, 16-, 32-, and 64-bit fixed-point processing—to set a new standard of performance for digital signal processors. The TigerSHARC processor’s Static Superscalar architecture lets the processor execute up to four instructions each cycle, performing 24 fixed-point (16-bit) operations or six floating-point operations.

FEATURES

300 MHz, 3.3 ns instruction cycle rate

6M bits of internal—on-chip—SRAM memory

19 mm × 19 mm (484-ball) or 27 mm × 27 mm

(625-ball) PBGA package

Dual computation blocks—each containing an ALU, a

multiplier, a shifter, and a register file

Dual integer ALUs, providing data addressing and pointer

manipulation

Integrated I/O includes 14-channel DMA controller, external

port, 4 link ports, SDRAM controller, programmable flag

pins, 2 timers, and timer expired pin for system integration

1149.1 IEEE compliant JTAG test access port for on-chip

emulation

On-chip arbitration for glueless multiprocessing with up to

8 TigerSHARC processors on a bus

BENEFITS

Provides high performance Static Superscalar DSP

operations, optimized for telecommunications infrastructure

and other large, demanding multiprocessor DSP

applications

Performs exceptionally well on DSP algorithm and I/O

benchmarks (see benchmarks in Table 1 and Table 2)

Supports low overhead DMA transfers between internal

memory, external memory, memory-mapped peripherals,

link ports, other DSPs (multiprocessor), and host

processors

Eases DSP programming through extremely flexible

instruction set and high-level language-friendly DSP architecture

Enables scalable multiprocessing systems with low

communications overhead