ADSP-BF538F中文资料亚德诺数据手册PDF规格书

GENERAL DESCRIPTION

The ADSP-BF538/ADSP-BF538F processors are members of the Blackfin family of products, incorporating the Analog Devices/Intel Micro Signal Architecture (MSA). Blackfin processors combine a dual-MAC state-of-the-art signal processing engine, the advantages of a clean, orthogonal RISC-like microprocessor instruction set, and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction set architecture.

FEATURES

Up to 500 MHz high performance Blackfin processor

Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,

40-bit shifter

RISC-like register and instruction model for ease of

programming and compiler friendly support

Advanced debug, trace, and performance monitoring

0.8 V to 1.2 V core VDD with on-chip voltage regulation

3.3 V tolerant I/O with specific 5 V tolerant pins

316-ball Pb-free mini-BGA package

MEMORY

148K bytes of on-chip memory:

16K bytes of instruction SRAM/cache

64K bytes of instruction SRAM

32K bytes of data SRAM

32K bytes of data SRAM/cache

4K bytes of scratchpad SRAM

512K bytes or 1M byte of flash memory (ADSP-BF538F parts

only)

Four dual-channel memory DMA controllers

Memory management unit providing memory protection

External memory controller with glueless support

for SDRAM, SRAM, flash, and ROM

Flexible memory booting options from SPI® and external

memory

PERIPHERALS

Parallel peripheral interface (PPI/GPIO)

supporting ITU-R 656 video data formats

Four dual-channel, full-duplex synchronous serial ports,

supporting 16 stereo I2S® channels

Two DMA controllers supporting 26 DMA channels

Controller area network (CAN) 2.0B controller

Three SPI-compatible ports

Three timer/counters with PWM support

Three UARTs with support for IrDA®

Two TWI controllers compatible with I2C® industry standard

Up to 54 general-purpose I/O pins (GPIO)

Real time clock, watchdog timer, and core timer

On-chip PLL capable of 0.5x To 64x frequency multiplication

Debug/JTAG interface