ADSP-2189M集成电路（IC）的DSP（数字信号处理器）规格书PDF中文资料

ADSP-2189M属于集成电路（IC）的DSP（数字信号处理器）。由亚德诺半导体技术有限公司制造生产的ADSP-2189MDSP（数字信号处理器）数字信号处理器是类似于微处理器或微控制器的器件，但区别在于其内部架构经修改，适用于对连续数据流连续执行以乘法和加法运算为主的算法，而不是以条件逻辑或大量并发进程为主的算法。该器件通常用于诸如音频或视频信号处理等应用。

GENERAL DESCRIPTION

The ADSP-2189M is a single-chip microcomputer optimized for digital signal processing (DSP) and other high speed numeric processing applications.

The ADSP-2189M combines the ADSP-2100 family base architecture (three computational units, data address generators and a program sequencer) with two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities, and on-chip program and data memory.

FEATURES

PERFORMANCE

13.3 ns Instruction Cycle Time @ 2.5 Volts (Internal),

75 MIPS Sustained Performance

Single-Cycle Instruction Execution

Single-Cycle Context Switch

3-Bus Architecture Allows Dual Operand Fetches in

Every Instruction Cycle

Multifunction Instructions

Power-Down Mode Featuring Low CMOS Standby

Power Dissipation with 200 CLKIN Cycle Recovery

from Power-Down Condition

Low Power Dissipation in Idle Mode

INTEGRATION

ADSP-2100 Family Code Compatible (Easy to Use Algebraic Syntax), with Instruction Set Extensions

192K Bytes of On-Chip RAM, Configured as 32K Words

On-Chip Program Memory RAM and 48K Words On-Chip Data Memory RAM

Dual Purpose Program Memory for Both Instruction

and Data Storage

Independent ALU, Multiplier/Accumulator and Barrel

Shifter Computational Units

Two Independent Data Address Generators

Powerful Program Sequencer Provides Zero Overhead

Looping Conditional Instruction Execution

Programmable 16-Bit Interval Timer with Prescaler

100-Lead LQFP

SYSTEM INTERFACE

Flexible I/O Structure Allows 2.5 V or 3.3 V Operation;

All Inputs Tolerate Up to 3.6 V, Regardless of Mode

16-Bit Internal DMA Port for High Speed Access to On-Chip Memory (Mode Selectable)

4 MByte Memory Interface for Storage of Data Tables

and Program Overlays (Mode Selectable)

8-Bit DMA to Byte Memory for Transparent Program

and Data Memory Transfers (Mode Selectable)

I/O Memory Interface with 2048 Locations Supports

Parallel Peripherals (Mode Selectable)

Programmable Memory Strobe and Separate I/O

Memory Space Permits “Glueless” System Design

Programmable Wait-State Generation

Two Double-Buffered Serial Ports with Companding

Hardware and Automatic Data Buffering

Automatic Booting of On-Chip Program Memory from

Byte-Wide External Memory, e.g., EPROM, or

Through Internal DMA Port

Six External Interrupts

13 Programmable Flag Pins Provide Flexible System

Signaling

UART Emulation through Software SPORT Reconfiguration

ICE-Port™ Emulator Interface Supports Debugging in

Final Systems