ADSP-21061KS-133集成电路（IC）的DSP（数字信号处理器）规格书PDF中文资料

ADSP-21061KS-133属于集成电路（IC）的DSP（数字信号处理器）。由亚德诺半导体技术有限公司制造生产的ADSP-21061KS-133DSP（数字信号处理器）数字信号处理器是类似于微处理器或微控制器的器件，但区别在于其内部架构经修改，适用于对连续数据流连续执行以乘法和加法运算为主的算法，而不是以条件逻辑或大量并发进程为主的算法。该器件通常用于诸如音频或视频信号处理等应用。

ADSP-2106x SHARC® DSP Microcomputer Family

GENERAL DESCRIPTION

The ADSP-21061 SHARC—Super Harvard Architecture Computer—is a signal processing microcomputer that offers new capabilities and levels of performance. The ADSP-21061 SHARC is a 32-bit processor optimized for high performance DSP applications. The ADSP-21061 builds on the ADSP-21000 DSP core to form a complete system-on-a-chip, adding a dualported on-chip SRAM and integrated I/O peripherals supported by a dedicated I/O bus.

SUMMARY

High performance signal processor for communications, graphics, and imaging applications

Super Harvard Architecture

Four independent buses for dual data fetch, instruction fetch, and nonintrusive I/O

32-bit IEEE floating-point computation units—multiplier, ALU, and shifter

Dual-ported on-chip SRAM and integrated I/O peripherals—a complete system-on-a-chip

Integrated multiprocessing features

KEY FEATURES—PROCESSOR CORE

50 MIPS, 20 ns instruction rate, single-cycle instruction execution

120 MFLOPS peak, 80 MFLOPS sustained performance

Dual data address generators with modulo and bit-reverse addressing

Efficient program sequencing with zero-overhead looping: single-cycle loop setup

IEEE JTAG Standard 1149.1 test access port and on-chip emulation

32-bit single-precision and 40-bit extended-precision IEEE floating-point data formats or 32-bit fixed-point data format

240-lead MQFP package, thermally enhanced MQFP, 225-ball plastic ball grid array (PBGA)

Lead (Pb) free packages. For more information, see Ordering Guide on Page 52.