ADRF5534BCPZN-RL中文资料亚德诺数据手册PDF规格书

GENERAL DESCRIPTION

The ADRF5534 is an integrated RF, front-end multichip module

designed for time division duplex (TDD) applications. The device

operates from 3.1 GHz to 4.2 GHz. The ADRF5534 is configured

with an LNA and a high-power, silicon, SPDT switch.

In the receive operation at 3.6 GHz, the LNA offers a low noise

figure (NF) of 1.3 dB and a high gain of 35.5 dB with a third order

input intercept point (IIP3) of −4 dBm.

In the transmit operation, the switch provides a low insertion loss

of 0.8 dB and handles a long-term evolution (LTE) average power

of 37 dBm for a full lifetime operation (8 dB peak to average ratio

(PAR)) and 39 dBm for a single event (<10 sec) LNA protection

operation.

FEATURES

► Integrated RF front end

► LNA and high-power silicon SPDT switch

► On-chip bias and matching

► Single-supply operation

► Gain: 35.5 dB typical at 3.6 GHz

► Gain flatness: 1.5 dB at 25°C across 400 MHz bandwidth

► Low noise figure: 1.3 dB typical at 3.6 GHz

► Low insertion loss: 0.8 dB typical at 3.6 GHz

► High-power handling at TCASE = 105°C

► Full lifetime

► LTE average power (8 dB PAR): 37 dBm

► Single event (<10 sec operation)

► LTE average power (8 dB PAR): 39 dBm

► High Input IP3: −4 dBm

► Low-supply current

► Receive operation: 120 mA typical at 5 V

► Transmit operation: 15 mA typical at 5 V

► Positive logic control

► 5 mm × 3 mm, 24-lead LFCSP package

APPLICATIONS

► Wireless infrastructure

► TDD massive multiple input and multiple output (MIMO) and

active antenna systems

► TDD-based communication systems