ADP1762ACPZ-1.0-R7集成电路（IC）的线性+开关稳压器规格书PDF中文资料

ADP1762ACPZ-1.0-R7属于集成电路（IC）的线性+开关稳压器。由亚德诺半导体技术有限公司制造生产的ADP1762ACPZ-1.0-R7稳压器 - 线性线性稳压器用于提供稳定的输出电压，无论负载电流、输入电压或环境因素如何变化，这些输出电压通常都要保持不变。它们的工作原理要求输入电压维持在高于所需的输出电压，而且要超出某个最小量，并且在工作时会将输入端的任何多余电压转换为热量。对于大多数应用而言，虽然这种稳压器的效率低于开关模式的稳压器，但它们通常更适合对噪声高度敏感的应用。

FEATURES

2 A maximum output current Low input voltage supply range

VIN = 1.10 V to 1.98 V, no external bias supply required Fixed output voltage range: VOUT_FIXED = 0.9 V to 1.5 V Adjustable output voltage range: VOUT_ADJ = 0.5 V to 1.5 V Ultralow noise: 2 μV rms, 100 Hz to 100 kHz Noise spectral density

4 nV/√Hz at 10 kHz 3 nV/√Hz at 100 kHz Low dropout voltage: 62 mV typical at 2 A load Operating supply current: 4.5 mA typical at no load ±1.5% fixed output voltage accuracy over line, load, and

temperature

Excellent power supply rejection ratio (PSRR) performance

62 dB typical at 10 kHz at 2 A load

46 dB typical at 100 kHz at 2 A load Excellent load/line transient response

Soft start to reduce inrush current

Optimized for small 10 μF ceramic capacitors Current-limit and thermal overload protection

Power-good indicator

Precision enable

16-lead, 3 mm × 3 mm LFCSP package

AEC-Q100 qualified for automotive applications

APPLICATIONS

Regulation to noise sensitive applications such as radio

frequency (RF) transceivers, analog-to-digital converter

(ADC) and digital-to-analog converter (DAC) circuits,

phase-locked loops (PLLs), voltage controlled oscillators

(VCOs) and clocking integrated circuits

Field-programmable gate array (FPGA) and digital signal processor (DSP) supplies

Medical and healthcare

Industrial and instrumentation