GENERAL DESCRIPTION

The ADP1752/ADP1753 are low dropout (LDO) CMOS linear regulators that operate from 1.6 V to 3.6 V and provide up to 800 mA of output current. These low VIN/VOUT LDOs are ideal for regulation of nanometer FPGA geometries operating from 2.5 V down to 1.8 V I/O rails, and for powering core voltages down to 0.75 V. Using an advanced proprietary architecture, they provide high power supply rejection ratio (PSRR) and low noise, and achieve excellent line and load transient response with only a small 4.7 µF ceramic output capacitor.

FEATURES

Maximum output current: 0.8 A

Input voltage range: 1.6 V to 3.6 V

Low shutdown current: <2 µA

Very low dropout voltage: 70 mV @ 0.8 A load

Initial accuracy: ±1

Accuracy over line, load, and temperature: ±2

7 fixed output voltage options with soft start 0.75 V to 2.5 V (ADP1752)

Adjustable output voltage option with soft start 0.75 V to 3.3 V (ADP1753)

High PSRR 65 dB @ 1 kHz 65 dB @ 10 kHz 54 dB @ 100 kHz

23 μV rms at 0.75 V output

Stable with small 4.7 µF ceramic output capacitor

Excellent load and line transient response

Current-limit and thermal overload protection

Power-good indicator

Logic-controlled enable

Reverse current protection

APPLICATIONS

Server computers

Memory components

Telecommunications equipment

Network equipment

DSP/FPGA/microprocessor supplies

Instrumentation equipment/data acquisition systems

ADP1752ACPZ-1.8-R7属于集成电路（IC） > 线性 + 开关稳压器。亚德诺半导体技术有限公司制造生产的ADP1752ACPZ-1.8-R7稳压器 - 线性线性稳压器用于提供稳定的输出电压，无论负载电流、输入电压或环境因素如何变化，这些输出电压通常都要保持不变。它们的工作原理要求输入电压维持在高于所需的输出电压，而且要超出某个最小量，并且在工作时会将输入端的任何多余电压转换为热量。对于大多数应用而言，虽然这种稳压器的效率低于开关模式的稳压器，但它们通常更适合对噪声高度敏感的应用。