ADN4667ARUZ集成电路（IC）的驱动器接收器收发器规格书PDF中文资料

ADN4667ARUZ属于集成电路（IC）的驱动器接收器收发器。由亚德诺半导体技术有限公司制造生产的ADN4667ARUZ驱动器，接收器，收发器该系列产品的主要功能是提供必需的硬件资源，以通过延长电缆或印制线进行通信。确切的功能会因所采用的通信协议而异，可能包括诸如瞬态抑制之类的功能，这些功能对于通信用途可能并非绝对必要，但对于可能的使用环境却是明智之选。

GENERAL DESCRIPTION

The ADN4667 is a quad, CMOS, low voltage differential signaling (LVDS) line driver offering data rates of over 400 Mbps (200 MHz) and ultralow power consumption. It features a flow through pinout for easy PCB layout and separation of input and output signals.

The device accepts low voltage TTL/CMOS logic signals and converts them to a differential current output of typically ±3.1 mA for driving a transmission medium such as a twisted pair cable. The transmitted signal develops a differential voltage of typi-cally ±310 mV across a termination resistor at the receiving end. This is converted back to a TTL/CMOS logic level by an LVDS receiver, such as the ADN4668.

The ADN4667 also offers active high and active low enable/ disable inputs (EN and EN). These inputs control all four drivers and turn off the current outputs in the disabled state to reduce the quiescent power consumption to typically 10 mW.

The ADN4667 and its companion LVDS receiver, the ADN4668, offer a new solution to high speed, point-to-point data trans-mission, and a low power alternative to emitter-coupled logic ECL) or positive emitter-coupled logic (PECL).

FEATURES

±15 kV ESD protection on output pins

400 Mbps (200 MHz) switching rates

Flow through pinout simplifies PCB layout

300 ps typical differential skew

400 ps maximum differential skew

1.7 ns maximum propagation delay

3.3 V power supply

±310 mV differential signaling

Low power dissipation (10 mW typical)

Interoperable with existing 5 V LVDS receivers

High impedance on LVDS outputs on power-down

Conforms to TIA/EIA-644 LVDS standards

Industrial operating temperature range: −40°C to +85°C

Available in surface-mount (SOIC) and low profile

TSSOP package

Qualified for automotive applications

APPLICATIONS

Backplane data transmission

Cable data transmission

Clock distribution