ADF4378数据手册ADI中文资料规格书

描述 Description

The ADF4378 is a high performance, ultra-low jitter, integer-Nphased locked loop (PLL) with an integrated voltage controlledoscillator (VCO) and system reference (SYSREF) retimer ideallysuited for data converter and mixed signal front end (MxFE) clockapplications. The high performance PLL has a −239 dBc/Hz: normalizedin-band phase noise floor, ultra-low 1/f noise, and a highphase/frequency detector (PFD) frequency that can achieve ultralowin-band noise and integrated jitter. The fundamental VCO andoutput divider of the ADF4378 generate frequencies from 800 MHzto 12.8 GHz. The ADF4378 integrates all necessary power-supplybypass capacitors, which saves board space on compact boards.

For multiple data converter and MxFE clock applications, theADF4378 simplifies clock alignment and calibration routines requiredwith other clock solutions by implementing the automaticreference to output synchronization feature, the matched referenceto output delays across process, voltage, and temperature feature,and the less than ±0.1 ps, jitter free reference to output delayadjustment capability feature.

The general-purpose pulse retimer feature allows for predictableand precise multichip clock and pulse alignment for SYSREF,SYNC, and multichip synchronization (MCS) architectures.JESD204B and JESD204C Subclass 1 solutions are supported bypairing the ADF4378 with an integrated circuit (IC) that distributespairs of reference and SYSREF signals. The pulse retimer featuresimplifies the system design by allowing the widely distributedSYSREF to only meet the slower reference frequency timing vs.the much more stringent output clock timing. Serial-peripheralinterface (SPI) selectable current-mode logic (CML)/low-voltagepositive/pseudo emitter-coupled logic (LVPECL) or low-voltage differentialsignaling (LVDS) SYSREF input and LVDS SYSREF outputallow CML to LVDS signal conversion, which simplifies clockand SYSREF alignment for various converters. The pulse retimerfeature also can be used with transceiver MCS signals and SYNCsignals for other ICs.

APPLICATIONS

High Performance Data Converter and MxFE ClockingWireless infrastructure (MC-GSM, 5G)Test and MeasurementFPGA with integrated data converters

特性 Features

• Output frequency range: 800 MHz to 12.8 GHz

• Jitter = 18 fsRMS (Integration BW: 100 Hz to 100 MHz)

• Jitter = 27 fsRMS (ADC SNR Method)

• Wideband Noise Floor: -160 dBc/Hz @12 GHz

• PLL Specifications:

• -239 dBc/Hz: Normalized In-Band Phase Noise Floor

• -147 dBc/Hz: Normalized In-Band 1/f Noise

• Phase Detector Frequency up to 500 MHz