ADF4112集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

ADF4112属于集成电路（IC）的时钟发生器PLL频率合成器。由亚德诺半导体技术有限公司制造生产的ADF4112时钟发生器，PLL，频率合成器时钟发生器、PLL 和频率合成器集成电路 (IC) 可为逻辑器件提供参考信号的稳定定时脉冲，这些器件包括计算机、微控制器、数据通信系统和图形/视频发生器。这些集成电路可能包括缓冲器、驱动器、分频器、倍频器、多路复用器、合成器、扇出分配器和预分频器。

GENERAL DESCRIPTION

The ADF4153 is a fractional-N frequency synthesizer that implements local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. It consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. There is a Σ-Δ based fractional interpolator to allow programmable fractional-N

division. The INT, FRAC, and MOD registers define an overall N divider (N= (INT+ (FRAC/MOD))). In addition, the 4-bit reference counter (R counter) allows selectable REFIN frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and a voltage controlled oscillator (VCO).

FEATURES

RF bandwidth to 4 GHz

2.7 V to 3.3 V power supply

Separate VP allows extended tuning voltage

Y version available: −40°C to +125°C

Programmable fractional modulus

Programmable charge pump currents

3-wire serial interface

Analog and digital lock detect

Power-down mode

Pin-compatible with ADF4110/ADF4111/ADF4112/ADF4113

and ADF4106

Consistent RF output phase

Loop filter design possible with ADIsimPLL

Qualified for automotive applications

APPLICATIONS

CATV equipment

Base stations for mobile radio (GSM, PCS, DCS, WiMAX,

SuperCell 3G, CDMA, W-CDMA)

Wireless handsets (GSM, PCS, DCS, CDMA, W-CDMA)

Wireless LANs, PMR

Communications test equipment