ADF4110集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

ADF4110属于集成电路（IC）的时钟发生器PLL频率合成器。由亚德诺半导体技术有限公司制造生产的ADF4110时钟发生器，PLL，频率合成器时钟发生器、PLL 和频率合成器集成电路 (IC) 可为逻辑器件提供参考信号的稳定定时脉冲，这些器件包括计算机、微控制器、数据通信系统和图形/视频发生器。这些集成电路可能包括缓冲器、驱动器、分频器、倍频器、多路复用器、合成器、扇出分配器和预分频器。

GENERAL DESCRIPTION

The ADF4110 family of frequency synthesizers can be used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. They consist of a low noise digital PFD (phase frequency detector), a precision charge pump, a programmable reference divider, programmable A and B counters, and a dual-modulus prescaler (P/P + 1). The A (6-bit) and B (13-bit) counters, in conjunction with the dual-modulus prescaler (P/P + 1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R counter) allows selectable REFIN frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO).

FEATURES

ADF4110: 550 MHz; ADF4111: 1.2 GHz; ADF4112: 3.0 GHz;

ADF4113: 4.0 GHz

2.7 V to 5.5 V power supply

Separate charge pump supply (VP) allows extended tuning

voltage in 3 V systems

Programmable dual-modulus prescaler 8/9, 16/17, 32/33,

64/65

Programmable charge pump currents

Programmable antibacklash pulse width

3-wire serial interface

Analog and digital lock detect

Hardware and software power-down mode

APPLICATIONS

Base stations for wireless radio (GSM, PCS, DCS, CDMA,

WCDMA)

Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA)

Wireless LANS

Communications test equipment

CATV equipment