ADC14L040CIVYSLASHNOPB中文资料德州仪器数据手册PDF规格书

1FEATURES

2• Single +3.3V Supply Operation

• Internal Sample-and-Hold

• Internal Reference

• Outputs 2.4V to 3.6V Compatible

• Duty Cycle Stabilizer

• Power Down Mode

APPLICATIONS

• Medical Imaging

• Instrumentation

• Communications

• Digital Video

KEY SPECIFICATIONS

• Resolution 14 Bits

• DNL ±0.5 LSB (typ)

• SNR (fIN = 10 MHz) 74 dB (typ)

• SFDR (fIN = 10 MHz) 90 dB (typ)

• Data Latency 7 Clock Cycles

• Power Consumption

– Operating 235 mW (typ)

– Power Down Mode 15 mW (typ)

DESCRIPTION

The ADC14L040 is a low power monolithic CMOS

analog-to-digital converter capable of converting

analog input signals into 14-bit digital words at 40

Megasamples per second (MSPS). This converter

uses a differential, pipeline architecture with digital

error correction and an on-chip sample-and-hold circuit to minimize power consumption while providing

excellent dynamic performance and a 150 MHz Full

Power Bandwidth. Operating on a single +3.3V power

supply, the ADC14L040 achieves 11.9 effective bits

at nyquist and consumes just 235 mW at 40 MSPS .

The Power Down feature reduces power consumption

to 15 mW.

The differential inputs provide a full scale differential

input swing equal to 2 times VREF with the possibility

of a single-ended input. Full use of the differential

input is recommended for optimum performance.

Duty cycle stabilization and output data format are selectable using a quad state function pin. The output

data can be set for offset binary or two's complement.

To ease interfacing to lower voltage systems, the

digital output driver power pins of the ADC14L040

can be connected to a separate supply voltage in the

range of 2.4V to the analog supply voltage.

This device is available in the 32-lead LQFP package

and will operate over the industrial temperature range

of −40°C to +85°C. An evaluation board is available

to ease the evaluation process.